User:Lidnariq/Mapper thoughts

EtherNES 1

A cartridge designed to provide ethernet in as simple a manner as practical, for use with Contiki. The design is intentionally similar to the 64NIC+ ethernet cartridge for the Commodore 64, even though the CS8900A is comparatively expensive.

Parts

• 1 × SST39SF010A, 128 KiB FLASH EEPROM, for booting
• 2 × AS6C1008, 128 KiB static RAM, one each for PRG RAM and CHR RAM
• 2 × 74'161, both set up to clear on reset.
  • One selects a 32 KiB slice of PRG
  • The other selects an 8 KiB slice of CHR RAM.
• 1 × 74'139
• 1 × 74'20
  • One NAND4 produces /INTSEL=NAND3(M2,/ROMSEL,A14,A13) and one decoder produces /RD6xxx, /WR6xxx, /RD7xxx, and /WR7xxx.
  • Other NAND4 produces /RD.
  • 2nd decoder selects RAM or ROM as appropriate.
• CS8900A or LAN91C96 already have drivers in the Contiki source tree
  • Other cheaper options: RTL8029, CP2200, ENC424J600, AX88796
• Ethernet transformer

Memory map

• $7xxx - CS8900A
  • http://www.cirrus.com/en/products/cs8900a.html
  • As with the C64 NIC, it does not present the memory-mappable portion of the CS8900A (why not?)
  • CS8900A does not have a separate I/O enable, just /IOR and /IOW; the address bus must be stable before these signals fall.
  • Why does the 64NIC+ not connect /IRQ ?
  • Obviously no DMA controller.
• READS from $6xxx - latching CPU A0..A3: PRG bank '161 (0,1,2,3 = ROM; C,D,E,F=RAM). Q3 determines which IC. Cleared on hardware reset.
• WRITES to $6xxx - latching CPU D0..D3: CHR bank '161
• $8000-$FFFF: PRG ROM or RAM, according to value at $7xxx.

Easier nametables, finer palette zones

Replace standard PPU nametable/attribute table with just one nametable, 32x30 tiles in size, each tile is 16x16 and uses 8x1 palette zones.

• using 32×30 allows us to reuse the scroll registers, rather than having fine X be magically somewhere else
• Each pattern table is thus 72 bytes (256 pixels × (18 bits/8 pixels)).
• Total memory for tiles in this manner: 18 KiB.

Pixel-perfect IRQs with clockslides

An interface to fire an IRQ at a specific X/Y coordinate that works by

• firing the IRQ approximately 14cy too early
• uses an injected clockslide to fix up any slop in initial IRQ firing time

Since there's already 3 pixels of intrinsic slop, the two axes can be X/2 and Y. Y is ever-so-slightly larger than a byte, so setting (255=scanline before NMI) and not allowing interrupts during the first 6 scanlines of vblank is an ok compromise.

Fake sprite 0 IRQs

1. IRQ when PPU address reads from a specific address, or
2. Snoop on CPU reads, monitoring for reads from $2002, and fire an IRQ