Talk:NES 2.0 Mapper 319: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
mNo edit summary
No edit summary
Line 5: Line 5:
Additionally, the description here (modifying overriding PRG A16 with CPU A14, instead of PRG A14 with CPU A14) really sounds like this description is a misdump. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 19:13, 15 May 2018 (MDT)
Additionally, the description here (modifying overriding PRG A16 with CPU A14, instead of PRG A14 with CPU A14) really sounds like this description is a misdump. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 19:13, 15 May 2018 (MDT)
:I have corrected the relative register location. Not sure what you mean by "misdumped description " in the second part. If the 16 KiB PRG-ROM bank bit 2 (4s) is modified, it's going to affect PRG A16, not A14. [[User:NewRisingSun|NewRisingSun]] ([[User talk:NewRisingSun|talk]]) 23:52, 15 May 2018 (MDT)
:I have corrected the relative register location. Not sure what you mean by "misdumped description " in the second part. If the 16 KiB PRG-ROM bank bit 2 (4s) is modified, it's going to affect PRG A16, not A14. [[User:NewRisingSun|NewRisingSun]] ([[User talk:NewRisingSun|talk]]) 23:52, 15 May 2018 (MDT)
::Or do you mean the ''ROM'' (and not the description) is misdumped, having the banks in a supposedly implausible order? I have not dumped the cart myself, and I am not going to assert bad dump status without having seen the board topology. [[User:NewRisingSun|NewRisingSun]] ([[User talk:NewRisingSun|talk]]) 00:10, 16 May 2018 (MDT)
:Or do you mean the ''ROM'' (and not the description) is misdumped, having the banks in a supposedly implausible order? I have not dumped the cart myself, and I am not going to assert bad dump status without having seen the board topology. [[User:NewRisingSun|NewRisingSun]] ([[User talk:NewRisingSun|talk]]) 00:10, 16 May 2018 (MDT)
:: That is exactly what I mean. There are a wealth of other boards which support both NROM-256 and NROM-128 by relaying or overriding CPU A14; this cart is unique in interpreting that signal as connecting to PRG A16 instead of A14. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 14:09, 16 May 2018 (MDT)

Revision as of 20:09, 16 May 2018

typo?

FCEUX's source in boards/hp898f.cpp swaps the location of the two registers relative to what's documented here. —Lidnariq (talk) 17:32, 15 May 2018 (MDT)

Additionally, the description here (modifying overriding PRG A16 with CPU A14, instead of PRG A14 with CPU A14) really sounds like this description is a misdump. —Lidnariq (talk) 19:13, 15 May 2018 (MDT)

I have corrected the relative register location. Not sure what you mean by "misdumped description " in the second part. If the 16 KiB PRG-ROM bank bit 2 (4s) is modified, it's going to affect PRG A16, not A14. NewRisingSun (talk) 23:52, 15 May 2018 (MDT)
Or do you mean the ROM (and not the description) is misdumped, having the banks in a supposedly implausible order? I have not dumped the cart myself, and I am not going to assert bad dump status without having seen the board topology. NewRisingSun (talk) 00:10, 16 May 2018 (MDT)
That is exactly what I mean. There are a wealth of other boards which support both NROM-256 and NROM-128 by relaying or overriding CPU A14; this cart is unique in interpreting that signal as connecting to PRG A16 instead of A14. —Lidnariq (talk) 14:09, 16 May 2018 (MDT)