UNROM 512: Difference between revisions
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Games that use this board include [[Battle Kid 2: Mountain of Torment]] and "Study Hall". | Games that use this board include [[Battle Kid 2: Mountain of Torment]] and "Study Hall". | ||
The example board in question is marked as follows: "Sealie Computing", "12/29/2011 revA", | The example board in question is marked as follows: "Sealie Computing", "12/29/2011 revA", "UNROM 512". The backside of the board was mislabeled with "ReproPak MMC3". | ||
The board includes 4x banks worth of full 8KB CHR ram (Configurable by jumpers) and 32x 16KB PRG banks. | |||
The board can be wired in a not flashable, or self flashable configuration. Mirroring can be selected between Horizontal, Vertical, and Mapper controlled One Screen. | |||
The board can be wired in a not flashable, or self flashable configuration. Mirroring can be | |||
selected between Horizontal, Vertical, and Mapper controlled One Screen. | |||
Bus conflicts are only present on the non-flashable configuration of the board. | Bus conflicts are only present on the non-flashable configuration of the board. | ||
Some images of the board: | |||
*[[Media:Unrom512_front_study_hall.jpg|Study Hall PCB Front]] | |||
*[[Media:Unrom512_front_bk2.jpg|Battle Kid 2 PCB Front]] | |||
*[[Media:Unrom512_back.jpg|PCB Back]] | |||
When board is not flashable: | When board is not flashable: | ||
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This configuration is not subject to bus conflicts | This configuration is not subject to bus conflicts | ||
</pre> | </pre> | ||
The Self-flashable configuration should be implemented according to the [http://www.microchip.com/wwwproducts/Devices.aspx?product=SST39SF040 SST39F040]'s datasheet. |
Revision as of 00:07, 3 April 2014
Games that use this board include Battle Kid 2: Mountain of Torment and "Study Hall".
The example board in question is marked as follows: "Sealie Computing", "12/29/2011 revA", "UNROM 512". The backside of the board was mislabeled with "ReproPak MMC3".
The board includes 4x banks worth of full 8KB CHR ram (Configurable by jumpers) and 32x 16KB PRG banks.
The board can be wired in a not flashable, or self flashable configuration. Mirroring can be selected between Horizontal, Vertical, and Mapper controlled One Screen.
Bus conflicts are only present on the non-flashable configuration of the board.
Some images of the board:
When board is not flashable:
Registers: --------------------------- Range,Mask: $8000-FFFF, $8000 $8000: [MCCP PPPP] M = One screen Mirroring select C = CHR RAM bank P = PRG ROM bank PRG Setup: --------------------------- $8000 $A000 $C000 $E000 +-------------------------------+ | $8000 | { -1} | +---------------+---------------+ CHR Setup: --------------------------- $0000 $1000 +-------+-------+ | $0000 | +-------+-------+
When board is self flashable:
Registers: --------------------------- Range,Mask: $8000-BFFF, $8000 $C000-FFFF, $C000 $8000: [.... ....] Write a sequence of bytes here for writing to the flash. The sequence is as follows (This code must exist in wram): Erase 4KB Flash Sector: $C000:$01, $9555:$AA $C000:$00, $AAAA:$55 $C000:$01, $9555:$80 $C000:$01, $9555:$AA $C000:$00, $AAAA:$55 $C000:BANK, ADDR:$30 (Where BANK is $00-1F, ADDR is $8000,$9000,$A000,$B000) Read the written location twice until you get $FF twice. Write a byte: $C000:$01, $9555:$AA $C000:$00, $AAAA:$55 $C000:$01, $9555:$A0 $C000:BANK, ADDR:DATA (Where BANK is $00-1F, ADDR is $8000-$BFFF, DATA is $00-$FF) Read the written location twice until you get DATA twice. $C000: [MCCP PPPP] M = One screen Mirroring select C = CHR RAM bank P = PRG ROM bank PRG Setup: --------------------------- $8000 $A000 $C000 $E000 +-------------------------------+ | $8000 | { -1} | +---------------+---------------+ CHR Setup: --------------------------- $0000 $1000 +-------+-------+ | $8000 | +-------+-------+
Here's a schematic of the board:
____ A14 ---------\ \ ) >--- ROM A14 377 O0 ------/____/ ____ A14 ---------\ \ ) >--- ROM A15 377 O1 ------/____/ ____ A14 ---------\ \ ) >--- ROM A16 377 O2 ------/____/ ____ A14 ---------\ \ ) >--- ROM A17 377 O3 ------/____/ ____ A14 ---------\ \ ) >--- ROM A18 377 O4 ------/____/ 16/32KB CRAM 377 O5 --[]--+-- CRAM A13 | VCC -----[]--+ 8KB CRAM 8/16KB CRAM VCC -----[]--+ | 377 O6 --[]--+-- CRAM A14 32KB CRAM ONE 377 O7 --[]--+ | VERTICAL | CHR A10 -[]--+-- CA10_VRAM | HORIZONTAL | CHR A11 -[]--+ Flash Locked 1 VCC ---[]--- ROM_/WE Flash Locked 2 P/CE --[]--- 377_CLK Flash Locked 3 P_RW --[]--- 377_/CE Flash Locked 4 GND ---[]--- ROM_/OE Flashable GND ---[]--- 377_/CE _________ A14 ----| A Y0|--- ROM_/WE P_RW ---| B Y1|--- 377_CLK | Y2| P_/CE --| G Y3| --------- 74*139 _________ P_RW ---| A Y0| GND ----| B Y1|--- ROM_/OE | Y2| P_/CE --| G Y3| ---------
The board is wired in one of the following configurations:
Not Flashable:
All 4 Flash Locked jumpers are soldered. Flashable jumper is not soldered. 74*139 is not mounted. This configuration is subject to bus conflicts
Flashable:
All 4 Flash Locked jumpers are not soldered. Flashable jumper is soldered. 74*139 is mounted. This configuration is not subject to bus conflicts
The Self-flashable configuration should be implemented according to the SST39F040's datasheet.