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| '''TEROM''' (NES-TEROM and HVC-TEROM) is a common board within the [[TxROM]] set. Like other TxROM boards, TEROM uses the [[MMC3|Nintendo MMC3]] ASIC.
| | #REDIRECT [[TxROM]] |
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| == Overview ==
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| * PRG ROM size: 32 KB
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| * PRG ROM bank size: 8 KB
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| * PRG RAM: None
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| * CHR capacity: 8, 16, 32, 64 KB ROM
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| * CHR bank size: 1 KB and 2 KB
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| * Nametable [[mirroring]]: Solder pads select horizontal, vertical or controlled by mapper.
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| * Subject to [[bus conflict]]s: No
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| == Banks ==
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| * CPU $8000-$9FFF (or $C000-$DFFF): 8 KB switchable PRG ROM bank
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| * CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
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| * CPU $C000-$DFFF (or $8000-$9FFF): 8 KB PRG ROM bank, fixed to the second-last bank
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| * CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
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| * PPU $0000-$07FF (or $1000-$17FF): 2 KB switchable CHR bank
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| * PPU $0800-$0FFF (or $1800-$1FFF): 2 KB switchable CHR bank
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| * PPU $1000-$13FF (or $0000-$03FF): 1 KB switchable CHR bank
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| * PPU $1400-$17FF (or $0400-$07FF): 1 KB switchable CHR bank
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| * PPU $1800-$1BFF (or $0800-$0BFF): 1 KB switchable CHR bank
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| * PPU $1C00-$1FFF (or $0C00-$0FFF): 1 KB switchable CHR bank
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| == Solder Pad Config ==
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| * Normal mode : 'CL1' connected, 'CL2' connected, 'H' disconnected, 'V' disconnected.
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| * [[DEROM]] backward compatibility mode with Horizontal mirroring : 'CL1' disconnected, 'CL2' disconnected, 'H' disconnected, 'V' connected.
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| * [[DEROM]] backward compatibility mode with Vertical mirroring : 'CL1' disconnected, 'CL2' disconnected, 'H' connected, 'V' disconnected.
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| Note : In DEROM backward compatibility mode, mirroring is hardwired and IRQs are disabled. However, the additionnal bankswitching modes available by the MMC3 that weren't available with the 109 chip used on DEROM boards are still present.
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| == Chips and pinouts ==
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| * PRG ROM - 256 kBit (32 KB x 8) (DIP-28)
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| ---_---
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| +5V - |01 28| - +5V
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| A12 - |02 27| - A14
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| A7 - |03 26| - A13
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| A6 - |04 25| - A8
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| A5 - |05 24| - A9
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| A4 - |06 23| - A11
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| A3 - |07 22| - /OE (connected to PRG /CE of MMC3)
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| A2 - |08 21| - A10
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| A1 - |09 20| - GND (/CE ?)
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| A0 - |10 19| - D7
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| D0 - |11 18| - D6
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| D1 - |12 17| - D5
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| D2 - |13 16| - D4
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| GND - |14 15| - D3
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| -------
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| This pinout is compatible with standard 27C256 EPROMs, no rewiring needed.
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| * CHR ROM - 512 kBit (64 KB x 8) (DIP-28)
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| ---_---
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| A15 - |01 28| - +5V
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| A12 - |02 27| - A14
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| A7 - |03 26| - A13
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| A6 - |04 25| - A8
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| A5 - |05 24| - A9
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| A4 - |06 23| - A11
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| A3 - |07 22| - /OE (/RD)
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| A2 - |08 21| - A10
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| A1 - |09 20| - /CE (CHR A13)
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| A0 - |10 19| - D7
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| D0 - |11 18| - D6
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| D1 - |12 17| - D5
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| D2 - |13 16| - D4
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| GND - |14 15| - D3
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| -------
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| This pinout is compatible with standard 27C512 EPROMs, as well with 27C256 (32 KB), 27C128 (16 KB) and 27C64 (8 KB). No rewiring is needed at all.
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| == See also ==
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| *[[MMC3|Nintendo MMC3]]
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