Sunsoft 4 pinout: Difference between revisions
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m (note that 29-31 are just an OR gate) |
m (fix my copypasta) |
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[[iNES Mapper 068|Sunsoft 4]]: 40-pin 0.6" PDIP | [[iNES Mapper 068|Sunsoft 4]]: 40-pin 0.6" PDIP | ||
.---\/---. | .---\/---. | ||
M2 -> | 01 40 | -- +5V | M2 -> | 01 40 | -- +5V | ||
/ROMSEL -> | 02 39 | <- R/W | /ROMSEL -> | 02 39 | <- R/W | ||
CPU A14 -> | 03 38 | <- CPU D6 | CPU A14 -> | 03 38 | <- CPU D6 | ||
CPU A13 -> | 04 37 | <- CPU D5 | CPU A13 -> | 04 37 | <- CPU D5 | ||
CPU A12 -> | 05 36 | <- CPU D4 | CPU A12 -> | 05 36 | <- CPU D4 | ||
PPU /A13 -> | 06 35 | <- CPU D3 | PPU /A13 -> | 06 35 | <- CPU D3 | ||
PPU A12 -> | 07 34 | <- CPU D2 | PPU A12 -> | 07 34 | <- CPU D2 | ||
PPU A11 -> | 08 33 | <- CPU D1 | PPU A11 -> | 08 33 | <- CPU D1 | ||
PPU A10 -> | 09 32 | <- CPU D0 | PPU A10 -> | 09 32 | <- CPU D0 | ||
?GND -> | 10 31 | <- PPU /RD | ?GND -> | 10 31 | <- OR A (PPU /RD) | ||
PRG /CE <- | 11 30 | <- SS4 /CHRSEL | PRG /CE <- | 11 30 | <- OR B (SS4 /CHRSEL) | ||
CHR A17 <- | 12 29 | -> CHR /CS | CHR A17 <- | 12 29 | -> OR Y (CHR /CS) | ||
CHR A16 <- | 13 28 | -> CIRAM /CS | CHR A16 <- | 13 28 | -> CIRAM /CS | ||
CHR A15 <- | 14 27 | -> SS4 /CHRSEL | CHR A15 <- | 14 27 | -> SS4 /CHRSEL | ||
CHR A14 <- | 15 26 | -> WRAM /CE | CHR A14 <- | 15 26 | -> WRAM /CE | ||
CHR A13 <- | 16 25 | -> | CHR A13 <- | 16 25 | -> PRG A14 | ||
CHR A12 <- | 17 24 | -> A15 | CHR A12 <- | 17 24 | -> PRG A15 | ||
CHR A11 <- | 18 23 | -> A16 | CHR A11 <- | 18 23 | -> PRG A16 | ||
CHR A10 <- | 19 22 | -> A17 | CHR A10 <- | 19 22 | -> PRG A17 | ||
GND -- | 20 21 | -> WRAM +CE | GND -- | 20 21 | -> WRAM +CE | ||
`--------' | `--------' | ||
Revision as of 21:08, 28 January 2013
Sunsoft 4: 40-pin 0.6" PDIP
.---\/---.
M2 -> | 01 40 | -- +5V
/ROMSEL -> | 02 39 | <- R/W
CPU A14 -> | 03 38 | <- CPU D6
CPU A13 -> | 04 37 | <- CPU D5
CPU A12 -> | 05 36 | <- CPU D4
PPU /A13 -> | 06 35 | <- CPU D3
PPU A12 -> | 07 34 | <- CPU D2
PPU A11 -> | 08 33 | <- CPU D1
PPU A10 -> | 09 32 | <- CPU D0
?GND -> | 10 31 | <- OR A (PPU /RD)
PRG /CE <- | 11 30 | <- OR B (SS4 /CHRSEL)
CHR A17 <- | 12 29 | -> OR Y (CHR /CS)
CHR A16 <- | 13 28 | -> CIRAM /CS
CHR A15 <- | 14 27 | -> SS4 /CHRSEL
CHR A14 <- | 15 26 | -> WRAM /CE
CHR A13 <- | 16 25 | -> PRG A14
CHR A12 <- | 17 24 | -> PRG A15
CHR A11 <- | 18 23 | -> PRG A16
CHR A10 <- | 19 22 | -> PRG A17
GND -- | 20 21 | -> WRAM +CE
`--------'
10 probably actually some control, not a supply pin
19 also connects to CIRAM A10
29,30,31 actually just an OR gate; for use with a 28-pin 128KB CHR-ROM
Reference: Naruko's notes
