SOROM: Difference between revisions
m (Created page with ''''SOROM''' (NES-SOROM and HVC-SOROM) is one of the less common boards within the SxROM subset. Like other SxROM boards, SOROM uses the Nintendo MMC1 ASIC, but becau...') |
(→Registers: shorter PRG RAM description) |
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| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode) | | +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode) | ||
+---- Select 8 KB PRG RAM bank | +---- Select 8 KB PRG RAM bank | ||
(0: volatile bank; 1: battery-backed bank) | |||
=== CHR bank 1 (internal, $C000-$DFFF) === | === CHR bank 1 (internal, $C000-$DFFF) === | ||
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Note: In 4KB CHR bank mode, the <code>S</code> bits in both CHR bank registers must be set to the same value, or the PRG RAM will be bankswitched as the PPU renders, causing disastrous results. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]]. | Note: In 4KB CHR bank mode, the <code>S</code> bits in both CHR bank registers must be set to the same value, or the PRG RAM will be bankswitched as the PPU renders, causing disastrous results. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]]. | ||
Revision as of 21:28, 9 December 2009
SOROM (NES-SOROM and HVC-SOROM) is one of the less common boards within the SxROM subset. Like other SxROM boards, SOROM uses the Nintendo MMC1 ASIC, but because it always uses CHR RAM, it uses a spare CHR address line to select between two PRG RAM chips, letting the program access up to 16 KB of PRG RAM.
Overview
- PRG ROM size: 128 or 256 KB (DIP-28/32 Nintendo pinout)
- PRG ROM bank size: 16 KB or 32 KB
- PRG RAM: 16 KB + battery*
- CHR capacity: 8 KB RAM
- CHR bank size: 8 KB or 4 KB
- Nametable mirroring: Controlled by mapper
- Subject to bus conflicts: No
Though this board utilizes a battery, it is connected to only one PRG RAM chip. The first RAM chip will not retain its data, but the second one will.
Solder pad config
- Second RAM chip retaining it's data : 'SL' disconnected, Battery, D1, D2 and R2 present.
- Both RAM chips not retaining any data : 'SL' connected, leave slots for Battery, D1, D2 and R2 free.
Registers
The behavior of this board differs from that of a typical MMC1 board in the use of the upper CHR address line:
CHR bank 0 (internal, $A000-$BFFF)
4bit0
-----
xSxxC
| |
| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
+---- Select 8 KB PRG RAM bank
(0: volatile bank; 1: battery-backed bank)
CHR bank 1 (internal, $C000-$DFFF)
4bit0 ----- xSxxC | | | +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode) +---- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
Note: In 4KB CHR bank mode, the S bits in both CHR bank registers must be set to the same value, or the PRG RAM will be bankswitched as the PPU renders, causing disastrous results. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.
