RP2C33 pinout: Difference between revisions
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(transcribe from electronics junker's schematic) |
(read datasheet for MB81416 DRAM: neither its A0 nor A7 inputs are used in its column select. Actually, I probably need an oscope to figure what signals the address lines are relaying) |
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[[Category:Pinouts]] | [[Category:Pinouts]] | ||
RP2C33 | [[Family Computer Disk System]] ASIC RP2C33 or RP2C33A: 64-pin shrink DIP (FDS files) | ||
.---\/---. | .---\/---. | ||
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CPU A9 -> | 07 58 | -> /CAS0 | CPU A9 -> | 07 58 | -> /CAS0 | ||
CPU A8 -> | 08 57 | <- R/W | CPU A8 -> | 08 57 | <- R/W | ||
PRG A6/ | PRG A6/13 <- | 09 56 | <- M2 | ||
PRG A5/ | PRG A5/12 <- | 10 55 | -> /IRQ | ||
PRG A4/ | PRG A4/11 <- | 11 54 | -> Audio | ||
PRG A3/ | PRG A3/10 <- | 12 53 | -- Gnd | ||
PRG A2/9 <- | 13 52 | -> SER OUT | |||
PRG A1/ | PRG A1/8 <- | 14 51 | <- SER IN | ||
PRG A0 <- | 15 50 | -> $4025W.2 (Disk 1=Read, 0=Write) | |||
CPU A7 -> | 16 49 | -> $4025W.1 (1=Reset transfer timing) | CPU A7 -> | 16 49 | -> $4025W.1 (1=Reset transfer timing) | ||
CPU A6 -> | 17 48 | -> $4025W.0 (1=Turn on motor) | CPU A6 -> | 17 48 | -> $4025W.0 (1=Turn on motor) | ||
Revision as of 17:34, 6 October 2016
Family Computer Disk System ASIC RP2C33 or RP2C33A: 64-pin shrink DIP (FDS files)
.---\/---.
/ROMSEL -> | 01 64 | -- +5V
CPU A14 -> | 02 63 | ?? XTAL2
CPU A13 -> | 03 62 | ?? XTAL1
CPU A12 -> | 04 61 | -- Gnd
CPU A11 -> | 05 60 | -> /RAS
CPU A10 -> | 06 59 | -> /CAS1
CPU A9 -> | 07 58 | -> /CAS0
CPU A8 -> | 08 57 | <- R/W
PRG A6/13 <- | 09 56 | <- M2
PRG A5/12 <- | 10 55 | -> /IRQ
PRG A4/11 <- | 11 54 | -> Audio
PRG A3/10 <- | 12 53 | -- Gnd
PRG A2/9 <- | 13 52 | -> SER OUT
PRG A1/8 <- | 14 51 | <- SER IN
PRG A0 <- | 15 50 | -> $4025W.2 (Disk 1=Read, 0=Write)
CPU A7 -> | 16 49 | -> $4025W.1 (1=Reset transfer timing)
CPU A6 -> | 17 48 | -> $4025W.0 (1=Turn on motor)
CPU A5 -> | 18 47 | <- $4032R.2 (1=Write protected)
CPU A4 -> | 19 46 | <- $4032R.1 (1=Disk not ready)
CPU A3 -> | 20 45 | <- $4032R.0 (1=Disk missing)
CPU A2 -> | 21 44 | <> EXT0
CPU A1 -> | 22 43 | <> EXT1
CPU A0 -> | 23 42 | <> EXT2
? ?? | 24 41 | <> EXT3
CPU D0 <> | 25 40 | <> EXT4
CPU D1 <> | 26 39 | <> EXT5
CPU D2 <> | 27 38 | <> EXT6
CPU D3 <> | 28 37 | <> EXT7/BATT
CPU D4 <> | 29 36 | <- PPU A10
CPU D5 <> | 30 35 | <- PPU A11
CPU D6 <> | 31 34 | -> CIRAM A10
GND -- | 32 33 | <> CPU D7
'--------'
Notes:
PRG address bus is multiplexed, as is typical for DRAMs.
EXT port can be written via $4026 and read via $4033
Transcribed from http://green.ap.teacup.com/junker/119.html
