PPU pinout: Difference between revisions
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* R/W, Dx, A0, A1, A2 are the signals from the [[CPU pin out and signal description|CPU]] | * R/W, Dx, A0, A1, A2 are the signals from the [[CPU pin out and signal description|CPU]] | ||
* /CS is generated by the [[74139]] on the mainboard to map the PPU in the range from $2000 to $3FFF | * /CS is generated by the [[74139]] on the mainboard to map the PPU in the range from $2000 to $3FFF | ||
* EXTx allows the combination of two PPUs - setting the "slave" bit in the "control" register causes the PPU to output | * EXTx allows the combination of two PPUs - setting the "slave" bit in the "control" register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color). | ||
* CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator, divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks, and divided by 6 for the colorburst frequency. | * CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator, divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks, and divided by 6 for the colorburst frequency. | ||
* /VBL is connected to the CPU's /NMI pin. (In a dual-PPU arrangement, the master /VBL is also connected to the slave's /SYNC input) | * /VBL is connected to the CPU's /NMI pin. (In a dual-PPU arrangement, the master /VBL is also connected to the slave's /SYNC input) | ||
Revision as of 07:13, 22 January 2013
Pin out
.--\/--.
R/W -> |01 40| -- +5
D0 <> |02 39| -> ALE
D1 <> |03 38| <> AD0
D2 <> |04 37| <> AD1
D3 <> |05 36| <> AD2
D4 <> |06 35| <> AD3
D5 <> |07 34| <> AD4
D6 <> |08 33| <> AD5
D7 <> |09 32| <> AD6
A2 -> |10 31| <> AD7
A1 -> |11 30| -> A8
A0 -> |12 29| -> A9
/CS -> |13 28| -> A10
EXT0 <> |14 27| -> A11
EXT1 <> |15 26| -> A12
EXT2 <> |16 25| -> A13
EXT3 <> |17 24| -> /RD
CLK -> |18 23| -> /WR
/VBL <- |19 22| <- /SYNC
GND -- |20 21| -> VOUT
`------'
Signal description
- R/W, Dx, A0, A1, A2 are the signals from the CPU
- /CS is generated by the 74139 on the mainboard to map the PPU in the range from $2000 to $3FFF
- EXTx allows the combination of two PPUs - setting the "slave" bit in the "control" register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color).
- CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator, divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks, and divided by 6 for the colorburst frequency.
- /VBL is connected to the CPU's /NMI pin. (In a dual-PPU arrangement, the master /VBL is also connected to the slave's /SYNC input)
- ALE tells the PPU to latch the ADx bus to generate the lower 8 bits of the PPU's address bus
- ADx is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus.
- A8..A13 are the top 6 bits of the PPU's address bus.
- /RD and /WR specify that the PPU is reading or writing to its private memory
- /SYNC forces vblank and restarts the frame. It is used in the NES to clear the screen when the console is reset either by the button or the CIC, and in a dual-PPU system to genlock the two PPUs together.
- VOUT is the shifted analog video output
