NES 2.0 submappers

Submapper is a term used in the NES 2.0 header for 4-bit codes designating functionally distinct variants of iNES mappers that cannot be distinguished by the memory size fields alone. Most emulators using iNES format distinguish these using CRC, SHA-1, or other hashes of the PRG ROM and CHR ROM, but this works only for games published prior to 1997, and not for new games on the same mapper.

As of early 2012, no submappers were officially defined, but in mid-2012, a drive to collect proposals began. One proposed general principle for backward compatibility is that submapper 0 be reserved for the default iNES behavior.

In September, Kevin Horton finally published a few definitions.

MMC1

Status: Draft (still needs clarification)

Most MMC1 boards wire all PRG ROM address lines A14-A18 to the mapper's output in a fairly predictable manner. Boards with CHR RAM wire PRG ROM A18 and the PRG RAM address lines to otherwise unused CHR bank outputs. But among boards designed to take a 32 KiB PRG ROM, some (SIROM) connect PRG ROM A14 to the MMC1's output, others (SEROM, SHROM, SH1ROM) directly to CPU A14.

0: Normal
1: Normal (SUROM, redundant with ROM size)
2: 16 KiB like SOROM, selected by bit 4 instead of SOROM standard bit 3?
3: MMC1A, where $E000 bit 4 offers no write protection (used by The Money Game and a few others; sometimes assigned to iNES Mapper 155)
4: Normal (SXROM, redundant with ROM and RAM size)

Source: MMC1 submappers

MMC3

Status: Draft

No submapper of mapper 4 is needed to distinguish MMC3 from MMC6, as any board with MMC6-sized PRG RAM will behave like MMC6. But there are two general kinds of MMC3 IRQ: the old style, which disables the IRQ when the latch is loaded with 0, and the new style, which produces an IRQ on every scanline. Some newer games rely on the new style behavior.

0: Normal
1: MMC6-style PRG RAM enable
2: Hardwired mirroring

Source: MMC3 submappers

iNES Mapper 034

0: Normal
1: Force NINA behavior even with no CHR ROM

Source: KH's submappers

iNES Mapper 071

Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have hardwired horizontal or vertical mirroring.

0: Normal
1: Single-screen mirroring (Fire Hawk)

The Quattro multicarts have been moved to mapper 232.

Source: KH's submappers

iNES Mapper 232

Similar to #71, with a separate register controlling which 64 KiB outer bank of the PRG ROM is used. This is used for the Quattro multicarts.

0: Normal
1: Swap the bits of the outer bank number (for the Aladdin Deck Enhancer versions)

iNES Mapper 078

Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have it set up to switch between horizontal and vertical mirroring, where the bit controls a mux between PA10 and PA11 whose output is sent to CIRAM A10.

1: Single-screen mirroring
2: Hardwired mirroring
3: Mapper-controlled H/V mirroring

Source: KH's submappers

VRC4

Konami's VRC4 mapper has five known variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper. These are spread across three mappers: two for 21, two for 25, and one for 23. There are theoretically 8*7 = 56 ways to wire these, but in all five extant possibilities, two adjacent address lines are used: A2 and A1, A0 and A1, A7 and A6, A2 and A3, and A3 and A2. All 14 combinations of two adjacent address lines easily fit in a submapper number:

3210
||||
|+++- Which address line corresponds is wired to the A1 in the VRC4a
+---- 0: Use next lower address line for VRC4a A2; 1: use next higher line

The values 0 (A0 and next lower) and 15 (A7 and next higher) are impossible.

The VRC4 article describes the ports by mapping them to the variant called "VRC4a" on that page, which uses A2 and A1, putting the four VRC IRQ ports (IRQ Latch low, IRQ Latch high, IRQ Control, and IRQ Acknowledge) at $F000, $F002, $F004, and $F006.

Nickname	A2	A1	Registers	iNES mapper	NES 2.0 submapper
VRC4a	A2	A1	$x000, $x002, $x004, $x006	21	9
VRC4b	A0	A1	$x000, $x002, $x001, $x003	25	1
VRC4c	A7	A6	$x000, $x040, $x080, $x0C0	21	14
VRC4d	A2	A3	$x000, $x008, $x004, $x00C	25	3
VRC4e	A3	A2	$x000, $x004, $x008, $x00C	23	10