NES 2.0 Mapper 260: Difference between revisions
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NewRisingSun (talk | contribs) (Swapping Mapper 260 and 290 assignments, because FCEUX had already assigned Mapper 260 to HPxx.) |
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[[Category:Multicart mappers | [[Category:Multicart mappers]]NES 2.0 Mapper 260 is used for HP10xx/HP20xx multicarts. It is a predecessor to [[INES Mapper 176|FK23C]], both in its register layout, and the fact that | ||
several multicarts exist in HPxx and FK23C versions. Its UNIF board name is '''BMC-HPxx'''. | |||
== | =Registers= | ||
==DIP Switch ($5000, read)== | |||
Mask: Unknown | |||
7654 3210 | |||
--------- | |||
.... ..DD | |||
++- DIP Switch Setting | |||
==Mode Register ($5000, write)== | |||
Mask: $5003 | |||
7654 3210 | |||
--------- | |||
L... .MMM | |||
| +++- Select banking mode | |||
| 0: MMC3: 256 KiB PRG, 256 KiB CHR | |||
| 1: MMC3: 256 KiB PRG, 128 KiB CHR | |||
| 2: MMC3: 128 KiB PRG, 256 KiB CHR | |||
| 3: MMC3: 128 KiB PRG, 128 KiB CHR | |||
| 4: NROM-128: 16 KiB PRG (mirrored at $8000 and $C000), 8 KiB CHR | |||
| 5: NROM-256: 32 KiB PRG, 8 KiB CHR | |||
| 6: CNROM: 32 KiB PRG, 16 KiB CHR | |||
| 7: CNROM: 32 KiB PRG, 32 KiB CHR | |||
+--------- 1= Lock, do not respond to further writes in the $5xxx range | |||
In MMC3 modes, the final PRG/CHR bank number is the result of masking the MMC3 bank register content according to the specified size (128 or 256 KiB) and OR'ing with | |||
the opposite-masked content of the PRG ($5001) and CHR ($5002) Base registers. In the CNROM modes, the inner bank comes from the CNROM Latch (one bit only in 16 KiB CHR mode, | |||
two bits in 32 KiB CHR mode) OR'ed with the opposite-masked content of the CHR ($5002) Base register. | |||
==PRG Base Register ($5001, write)== | |||
Mask: $5003 | |||
7654 3210 | |||
--------- | |||
..PP PPPP | |||
++-++++- Select 16 KiB PRG Base | |||
==CHR Base Register ($5002, write)== | |||
Mask: $5003 | |||
7654 3210 | |||
--------- | |||
.PPP PPPP | |||
+++-++++- Select 8 KiB CHR Base | |||
==CNROM Latch ($8000-$FFFF, write)== | |||
Mask: $8000 | Mask: $8000 | ||
7654 3210 | |||
--------- | |||
.... ..LL | |||
++- Select 8 KiB Inner CHR Bank in CNROM modes | |||
==MMC3-compatible registers ($8000-$FFFF, write)== | |||
Mask: $E001 | |||
$8000, $8001, $A000, $A001, $C000, $C001, $E000, $E001: As normal [[MMC3]]. | |||
=Notes= | |||
* The | * The description of CNROM mode is based on the FCEUX source code. None of the available ROM images actually use it; instead, the games on those multicarts that originally were CNROM have all been modified to directly modify the CHR Base register ($5002). | ||
* WRAM at $6000-$7FFF is supported. | |||
* The KY6009 6-in-1 multicart menu times its music by polling $2002 bit 7 but does not take the [[NMI#Race_condition|race condition]] into account. As a result, its music is audibly slowed down irregularly when played on an original NES/Famicom console. | |||
Revision as of 14:46, 2 March 2018
NES 2.0 Mapper 260 is used for HP10xx/HP20xx multicarts. It is a predecessor to FK23C, both in its register layout, and the fact that several multicarts exist in HPxx and FK23C versions. Its UNIF board name is BMC-HPxx.
Registers
DIP Switch ($5000, read)
Mask: Unknown
7654 3210
---------
.... ..DD
++- DIP Switch Setting
Mode Register ($5000, write)
Mask: $5003 7654 3210 --------- L... .MMM | +++- Select banking mode | 0: MMC3: 256 KiB PRG, 256 KiB CHR | 1: MMC3: 256 KiB PRG, 128 KiB CHR | 2: MMC3: 128 KiB PRG, 256 KiB CHR | 3: MMC3: 128 KiB PRG, 128 KiB CHR | 4: NROM-128: 16 KiB PRG (mirrored at $8000 and $C000), 8 KiB CHR | 5: NROM-256: 32 KiB PRG, 8 KiB CHR | 6: CNROM: 32 KiB PRG, 16 KiB CHR | 7: CNROM: 32 KiB PRG, 32 KiB CHR +--------- 1= Lock, do not respond to further writes in the $5xxx range
In MMC3 modes, the final PRG/CHR bank number is the result of masking the MMC3 bank register content according to the specified size (128 or 256 KiB) and OR'ing with the opposite-masked content of the PRG ($5001) and CHR ($5002) Base registers. In the CNROM modes, the inner bank comes from the CNROM Latch (one bit only in 16 KiB CHR mode, two bits in 32 KiB CHR mode) OR'ed with the opposite-masked content of the CHR ($5002) Base register.
PRG Base Register ($5001, write)
Mask: $5003 7654 3210 --------- ..PP PPPP ++-++++- Select 16 KiB PRG Base
CHR Base Register ($5002, write)
Mask: $5003 7654 3210 --------- .PPP PPPP +++-++++- Select 8 KiB CHR Base
CNROM Latch ($8000-$FFFF, write)
Mask: $8000
7654 3210
---------
.... ..LL
++- Select 8 KiB Inner CHR Bank in CNROM modes
MMC3-compatible registers ($8000-$FFFF, write)
Mask: $E001 $8000, $8001, $A000, $A001, $C000, $C001, $E000, $E001: As normal MMC3.
Notes
- The description of CNROM mode is based on the FCEUX source code. None of the available ROM images actually use it; instead, the games on those multicarts that originally were CNROM have all been modified to directly modify the CHR Base register ($5002).
- WRAM at $6000-$7FFF is supported.
- The KY6009 6-in-1 multicart menu times its music by polling $2002 bit 7 but does not take the race condition into account. As a result, its music is audibly slowed down irregularly when played on an original NES/Famicom console.
