MMC2 pinout: Difference between revisions
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m (CIRAM A10 is an output) |
m (switch to using CPU/PRG and PPU/CHR for extra clarity) |
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Line 5: | Line 5: | ||
.----\/----. | .----\/----. | ||
GND - |XX XX| - +5V | GND - |XX XX| - +5V | ||
M2 (n) -> |01 40| - +5V | |||
CPU A14 (n) -> |02 39| - GND | |||
CPU A13 (n) -> |03 38| -> CIRAM A10 (n) | |||
PRG A15 (r) <- |04 37| -> CHR A15 (r) | PRG A15 (r) <- |04 37| -> CHR A15 (r) | ||
PRG A14 (r) <- |05 36| -> CHR A12 (r) | PRG A14 (r) <- |05 36| -> CHR A12 (r) | ||
CPU A12 (s) -> |06 35| -> CHR A14 (r) | |||
PRG A13 (r) <- |07 34| <- | PRG A13 (r) <- |07 34| <- PPU A12 (n) | ||
PRG A16 (r) <- |08 33| -> CHR A13 (r) | PRG A16 (r) <- |08 33| -> CHR A13 (r) | ||
PRG /CE (r) <- |09 32| -> CHR A16 (r) | PRG /CE (r) <- |09 32| -> CHR A16 (r) | ||
CPU D4 (s) -> |10 31| <- PPU A8 (s) | |||
CPU D3 (s) -> |11 30| <- PPU A5 (s) | |||
CPU D0 (s) -> |12 29| <- PPU A9 (s) | |||
CPU D1 (s) -> |13 28| <- PPU A4 (s) | |||
CPU D2 (s) -> |14 27| <- PPU A11 (s) | |||
CPU R/W (n) -> |15 26| <- PPU A3 (s) | |||
/ROMSEL (n) -> |16 25| <- PPU A7 (s) | |||
PPU /RD (s) -> |17 24| <- PPU A2 (s) | |||
PPU A0 (s) -> |18 23| <- PPU A10 (s) | |||
PPU A6 (s) -> |19 22| <- PPU A1 (s) | |||
GND - |20 21| <- | GND - |20 21| <- PPU A13 (s) | ||
`----------' | `----------' | ||
Revision as of 00:07, 24 July 2012
MMC2 Chip: (40/42 pin shrink-DIP)
Modern revisions of the chip are labelled MMC2-L and are 42 pin instead of 40 pin.
.----\/----. GND - |XX XX| - +5V M2 (n) -> |01 40| - +5V CPU A14 (n) -> |02 39| - GND CPU A13 (n) -> |03 38| -> CIRAM A10 (n) PRG A15 (r) <- |04 37| -> CHR A15 (r) PRG A14 (r) <- |05 36| -> CHR A12 (r) CPU A12 (s) -> |06 35| -> CHR A14 (r) PRG A13 (r) <- |07 34| <- PPU A12 (n) PRG A16 (r) <- |08 33| -> CHR A13 (r) PRG /CE (r) <- |09 32| -> CHR A16 (r) CPU D4 (s) -> |10 31| <- PPU A8 (s) CPU D3 (s) -> |11 30| <- PPU A5 (s) CPU D0 (s) -> |12 29| <- PPU A9 (s) CPU D1 (s) -> |13 28| <- PPU A4 (s) CPU D2 (s) -> |14 27| <- PPU A11 (s) CPU R/W (n) -> |15 26| <- PPU A3 (s) /ROMSEL (n) -> |16 25| <- PPU A7 (s) PPU /RD (s) -> |17 24| <- PPU A2 (s) PPU A0 (s) -> |18 23| <- PPU A10 (s) PPU A6 (s) -> |19 22| <- PPU A1 (s) GND - |20 21| <- PPU A13 (s) `----------'
(r) - this pin connects to the ROM chips only (n) - this pin connects to the NES connector only (s) - this pin is shared with the NES connector and ROM chips (w) - this pin connects to the WRAM only