MMC1 pinout

MMC1 Chip: (24 pin shrink-DIP)

Comes in several varieties: 'MMC1', 'MMC1A', and 'MMC1B2'

                 .--\/--.
  PRG A14 (r) <- |01  24|  - +5V
  PRG A15 (r) <- |02  23| <- M2 (n)
  PRG A16 (r) <- |03  22| <- CPU A13 (s)
  PRG A17 (r) <- |04  21| <- CPU A14 (n)
  PRG /CE (r) <- |05  20| <- /ROMSEL (n)
  WRAM CE (w) <- |06  19| <- CPU D7 (s)
  CHR A12 (r) <- |07  18| <- CPU D0 (s)
  CHR A13 (r) <- |08  17| <- CPU R/W 
  CHR A14 (r) <- |09  16| -> CIRAM A10 (n)
  CHR A15 (r) <- |10  15| <- PPU A12 (n)
  CHR A16 (r) <- |11  14| <- PPU A11 (s)
          GND  - |12  13| <- PPU A10 (s)
                 `------'
 
 (r) - this pin connects to the ROM chips only
 (n) - this pin connects to the NES connector only
 (s) - this pin is shared with the NES connector and ROM chips
 (w) - this pin connects to the WRAM only

As with many other ASIC mappers, parts of the pinout are often repurposed:

SEROM, SHROM, SH1ROM: only supports 32kiB at a time banking

                .--\/--.
         n/c <- |01  24|  - +5V
 PRG A15 (r) <- |02  23| <- M2 (n)

       CPU A14 (n) -> PRG A14 (r)

SNROM: loses CHR banking for a PRG-RAM disable

          n/c <- |08  17| <- CPU R/W 
          n/c <- |09  16| -> CIRAM A10 (n)
          n/c <- |10  15| <- PPU A12 (n)
 WRAM /CE (w) <- |11  14| <- PPU A11 (s)
          GND  - |12  13| <- PPU A10 (s)
                 `------'

SOROM: loses CHR banking for PRG-RAM banking

          n/c <- |08  17| <- CPU R/W 
          n/c <- |09  16| -> CIRAM A10 (n)
 WRAM A14 (w) <- |10  15| <- PPU A12 (n)
          n/c <- |11  14| <- PPU A11 (s)
          GND  - |12  13| <- PPU A10 (s)
                 `------'

SOROM is actually implemented using the WRAMs' /CE inputs and an inverter to select only one RAM at a time.

SUROM: loses CHR banking for PRG-ROM banking

          n/c <- |08  17| <- CPU R/W 
          n/c <- |09  16| -> CIRAM A10 (n)
          n/c <- |10  15| <- PPU A12 (n)
  PRG A18 (r) <- |11  14| <- PPU A11 (s)
          GND  - |12  13| <- PPU A10 (s)
                 `------'

SXROM: loses CHR banking for PRG-ROM and PRG-RAM banking

          n/c <- |08  17| <- CPU R/W 
 WRAM A14 (w) <- |09  16| -> CIRAM A10 (n)
 WRAM A15 (w) <- |10  15| <- PPU A12 (n)
  PRG A18 (r) <- |11  14| <- PPU A11 (s)
          GND  - |12  13| <- PPU A10 (s)
                 `------'

EVENT: loses CHR banking for more complicated PRG-ROM banking and timer control

    PRG2 A15 <- |08  17| <- CPU R/W 
    PRG2 A16 <- |09  16| -> CIRAM A10 (n)
     PRG SEL <- |10  15| <- PPU A12 (n)
 TIMER RESET <- |11  14| <- PPU A11 (s)
         GND  - |12  13| <- PPU A10 (s)
                `------'

Since the PPU A12 input's only purpose is to switch the CHR A12 .. A16 outputs, it's not clear why Nintendo didn't tie the MMC1's PPU A12 input low and connect CHR A12 directly to PPU A12. Doing so would have cost nothing (the ability to swap the two nametables is already granted through the register at $2000), would have prevented mistakes (unless the same value is in both CHR registers, 4KB mode causes erratic switching of bank during rendering), and would have freed up another bit of control.