CPU variants: Difference between revisions
(Adds new ceramic RP2A03 image.) |
(eugene-s tells me that all four revisions of the 6561xx-2s as well as 6561F-1 have the correct duty cycles, and that revision F is oldest, so it's unlikely that QFP80 6561 duties were ever wrong) |
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| UM6557 || Believed to be a 100% duplicate of UA6527, for use in SECAM regions. | | UM6557 || Believed to be a 100% duplicate of UA6527, for use in SECAM regions. | ||
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| UM6561xx-1 || NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known | | UM6561xx-1 || NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known. | ||
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| UM6561xx-2 || NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known | | UM6561xx-2 || NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known. | ||
F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | ||
Revision as of 14:28, 7 April 2024
Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:
| RP2A03 | M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. APU Frame Counter not restarted on reset. Has broken and disabled programmable interval timer on-die. Pin 30 connects to nothing. Other differences?
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| RP2A03E | Pin 30 is /RDY - combined with internal signals before feeding to internal 6502 +RDY.
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| RP2A03G | Reference model. Pin 30 enables a CPU test mode. Later runs introduced a DMC DMA bug [2].
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| RP2A03H | No known differences from late RP2A03G.
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| RP2A04 | Not actually a CPU at all, just a jumper in a 40-pin PDIP
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| RP2A07 | Input clock divider is 16. M2 duty cycle is 19/32 [3]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Pin 30 connects to 6502 /RDY input.
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| RP2A07A | no known differences relative to 2A07letterless
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| MG-N-501 |  Unlike early UA6527, DMC works
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| MG-P-501 | Micro Genius-made clone. Die has the same (UMC) © Ⓜ B6167F marking as a UA6527P.
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| UA6527 | UMC-made clone of 2A03G. Has swapped pulse channel duty cycles.
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| UA6527P | UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527.
Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [4]. Additionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles) One revision has (UMC) © Ⓜ B6167F 1989 09 on the die. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for DMC DMA implicit-stop glitches (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle.
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| UA6527PQ | 
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| UA6540 | UMC-made clone of 2A07 [5]. Has swapped pulse duty cycles.
Subsequent research implies this is identical to the early 6527P - NTSC tuning tables, ÷16 CPU divider. [6]
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| UM6557 | Believed to be a 100% duplicate of UA6527, for use in SECAM regions. | ||||||
| UM6561xx-1 | NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known. | ||||||
| UM6561xx-2 | NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known.
F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. AF revision observed to have incorrect ASR #imm ($4B) behavior, but other stable illegal instructions work properly.
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| 1818N | ??-made NES-on-a-chip, NTSC timing.
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| T1818P | ??-made NES-on-a-chip[[7]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | ||||||
| TA-03N | ??-made die-mask clone of 2A03G. Chip underside also has two codes of currently unknown purpose. Pin 30 activates CPU Test Mode like on 2A03G. Illegal opcodes differ from a legitimate 2A03G, although their functions are not understood.
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| TA-03NP | ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15?
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| TA-03NP1 | ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
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| PM03 | Gradiente-made clone of 2A03G. [8]
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| GS870007 | (Goldstar??)-made clone of 2A03 - has functioning decimal mode? [9]
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| KC-6005 | Found in MT777-DX famiclone, behaves exactly like UA6527P
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| 6005B | 
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| 2011 | 
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| “2A03E” | Both with and without USC insignia
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| KP2B03E | 
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| 6527-21 | 
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| 6527P |  
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| HA6527P |  
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| 6527P-SS-P03 | 
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| 6527UP-8 | 
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| 6527AP |  
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| SL/WH6527AP | 
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| SNC6527P | 
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| XYZ-6783 | Lacks tonal noise mode like original RP2A03, but resets APU Frame Counter on console reset like 2A03E/2A03G. Otherwise behaves like letterless RP2A03.
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| 6538N | ??-made CPU, despite the part number being similar to UMC PPU. Has inverted duty cycles like UA6527. DPCM works.
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If you know of other differences or other revisions, please add them!
