CPU Test Mode

Pin 30 on the 2A03 provides special functionality in some revisions of the chip and is normally grounded.

2A03E

The schematic for the Playchoice 10 permits the supervisor CPU to stop the 2A03E by driving pin 30 high, and then can reset it (both driving pin 30 low and 2A03E /RESET low). Testing pin 30 by itself (with a button) just crashes the CPU. It's unclear if it can be used for anything else.

Subsequent research has discovered that this is /RDY and combined with the CPU's internal DMA units RDY signal; driving this high will stall the CPU.

2A07A

Pin 30 is an external /RDY input, its inverse effectively being ANDed together with the internal signal from the 2A03's DMA hardware. It's suspected the 2A03E is actually the same, but we don't have any evidence yet.

2A03G / 2A03H Test Mode

Pin 30 of the 2A03G and 2A03H can be asserted to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:

R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume) 
                      and T=triangle (anywhere from 0 to 15)
R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel (same as value written to $4011)
W$401A: [L..T TTTT] - set state of triangle's sequencer to T, and lock all channels if L=1
                      (pulse+noise always output current volume, triangle/DPCM no longer advance)

Test mode disconnects the external CPU bus from the internal bus when reading from any of $4000-401F, just as normally happens when reading from $4015; this is what disables the joypads, by preventing the CPU from seeing the value they put on the bus. Test mode also causes the CPU to continue outputting M2 while held in reset.

Connecting pin 30 to CPU A3 allows the test and controller registers to coexist, at the cost of increased likelihood of DMC DMA corruption when the CPU is reading from $4000-401F (see DMA register conflicts). Because the state of A3 is effectively random when reset begins and because the address lines go high impedance during reset, a weak pulldown (10k Ohm) should be used to prevent pin 30 from floating while reset is held and restore standard M2-during-reset behavior.

2A03

Pin 30 has no function in the original version of the 2A03.

See also

• Forum: Breaking NES apart
• See: File:Apu address.jpg
• See: CPU pin out and signal description