Visual6502wiki/6502 increment PC control: Difference between revisions
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The 6502 Program Counter has a dedicated | The 6502 Program Counter (PC) has a dedicated incrementing circuit, which has to be able to increment across all 16 bits of the PC in a single cycle. | ||
It (almost) always increments during an instruction fetch cycle, to fetch a possible operand, but in general the decision whether or not to increment is a complex one. The exception to incrementing during fetch is [http://visual6502.org/JSSim/expert.html?graphics=f&loglevel=2&steps=30&logmore=nmi,379,sync&nmi0=20 illustrated here] - in the cycle when an interrupt is recognised, the instruction fetch occurs but the instruction is ignored and the PC increment is suppressed in order that the PC value can be stacked. | It (almost) always increments during an instruction fetch cycle, to fetch a possible operand, but in general the decision whether or not to increment is a complex one. The exception to incrementing during fetch is [http://visual6502.org/JSSim/expert.html?graphics=f&loglevel=2&steps=30&logmore=nmi,379,sync&nmi0=20 illustrated here] - in the cycle when an interrupt is recognised, the instruction fetch occurs but the instruction is ignored and the PC increment is suppressed in order that the PC value can be stacked. | ||
Latest revision as of 00:52, 10 February 2023
The 6502 Program Counter (PC) has a dedicated incrementing circuit, which has to be able to increment across all 16 bits of the PC in a single cycle.
It (almost) always increments during an instruction fetch cycle, to fetch a possible operand, but in general the decision whether or not to increment is a complex one. The exception to incrementing during fetch is illustrated here - in the cycle when an interrupt is recognised, the instruction fetch occurs but the instruction is ignored and the PC increment is suppressed in order that the PC value can be stacked.
As it happens, some of the logic implementing that decision is absent from Balazs' schematic, probably because of a bad patch in the die photograph. It also happens to use some unusual NMOS logic techniques.
Here's the layout, as rendered by visual6502's JSSim:
The highlighted signal bottom centre is the negative-sense signal "dpc36_#IPC", and the highlighted signal near the middle is "short-circuit-branch-add"
Here's a diagram of the final few logic stages, which react to page-crossing branches, taken branches, single-byte instructions, interrupt handing (D1x1) and stalled cycles (use of RDY):
Note that the exclusive OR is implemented as a modified multiplexor which includes the subsequent AND function. The modification ensures that the AND's pulldown doesn't affect the signal notALUcout (node 206) which is used elsewhere, by pulling it down through the multiplexor's pass transistors.
Here's a transistor level view covering most of the same circuit:
