User:Ddribin/PPU Sandbox: Difference between revisions
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; Bit 7 - NMI<nowiki>:</nowiki> NMI Enable | ; Bit 7 - NMI<nowiki>:</nowiki> NMI Enable | ||
Setting NMI to one causes an NMI to be generated at the start of the vertical blanking interval | |||
; Bit 6 - MSS<nowiki>:</nowiki> Master/Slave Enable | ; Bit 6 - MSS<nowiki>:</nowiki> Master/Slave Enable | ||
Has no effect on the NES. | |||
; Bit 5 - SSZ<nowiki>:</nowiki> Sprite Size | ; Bit 5 - SSZ<nowiki>:</nowiki> Sprite Size | ||
0: 8x8; 1: 8x16 | |||
; Bit 4 - BPT<nowiki>:</nowiki> Background Pattern Table | ; Bit 4 - BPT<nowiki>:</nowiki> Background Pattern Table | ||
Background pattern table address (0: $0000; 1: $1000) | |||
; Bit 3 - SPT<nowiki>:</nowiki> Sprite Pattern Table | ; Bit 3 - SPT<nowiki>:</nowiki> Sprite Pattern Table | ||
Sprite pattern table address for 8x8 sprites (0: $0000; 1: $1000) | |||
; Bit 2 - VDN<nowiki>:</nowiki> VRAM Increment Down | ; Bit 2 - VDN<nowiki>:</nowiki> VRAM Increment Down | ||
VRAM address increment per CPU read/write of PPUDATA (0: increment by 1, going across; 1: increment by 32, going down) | |||
; Bits 1, 0 - NTA1 and NTA0<nowiki>:</nowiki> Base Nametable Address | ; Bits 1, 0 - NTA1 and NTA0<nowiki>:</nowiki> Base Nametable Address | ||
{| class="wikitable" style="text-align:center;" border="1" cellspacing="0" cellpadding="3" | {| class="wikitable" style="text-align:center;" border="1" cellspacing="0" cellpadding="3" | ||
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| 1 || 1 || $2C00 (Nametable 3) | | 1 || 1 || $2C00 (Nametable 3) | ||
|} | |} | ||
== PPUSTATUS - The PPU Status Register == | |||
Revision as of 14:37, 25 December 2009
PPUCTRL - The PPU Control Register
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|
| $2000 | NMI | MSS | SSZ | BPT | SPT | VDN | NTA1 | NTA0 |
| Read/Write | W | W | W | W | W | W | W | W |
| Initial Value | X | X | X | X | X | X | X | X |
- Bit 7 - NMI: NMI Enable
Setting NMI to one causes an NMI to be generated at the start of the vertical blanking interval
- Bit 6 - MSS: Master/Slave Enable
Has no effect on the NES.
- Bit 5 - SSZ: Sprite Size
0: 8x8; 1: 8x16
- Bit 4 - BPT: Background Pattern Table
Background pattern table address (0: $0000; 1: $1000)
- Bit 3 - SPT: Sprite Pattern Table
Sprite pattern table address for 8x8 sprites (0: $0000; 1: $1000)
- Bit 2 - VDN: VRAM Increment Down
VRAM address increment per CPU read/write of PPUDATA (0: increment by 1, going across; 1: increment by 32, going down)
- Bits 1, 0 - NTA1 and NTA0: Base Nametable Address
| NTA1 | NTA0 | Base VRAM Address |
|---|---|---|
| 0 | 0 | $2000 (Nametable 0) |
| 0 | 1 | $2400 (Nametable 1) |
| 1 | 0 | $2800 (Nametable 2) |
| 1 | 1 | $2C00 (Nametable 3) |
