Talk:VRC7 audio: Difference between revisions

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:Yeah, I looked it up afterwards when I realized this info should be in the datasheet. I plan to do some testing of this later to make sure the numbers are good enough; the earlier ballpark guesses were just from trying things until it worked-- I believe some of the registers finish updating faster than others, so my guesses were a bit off from the recommended times, apparently. - [[User:Rainwarrior|Rainwarrior]] 20:44, 15 May 2012 (PDT)
:Yeah, I looked it up afterwards when I realized this info should be in the datasheet. I plan to do some testing of this later to make sure the numbers are good enough; the earlier ballpark guesses were just from trying things until it worked-- I believe some of the registers finish updating faster than others, so my guesses were a bit off from the recommended times, apparently. - [[User:Rainwarrior|Rainwarrior]] 20:44, 15 May 2012 (PDT)
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Revision as of 20:43, 6 September 2013

The OPLL datasheet (transcribed here- http://www.smspower.org/maxim/Documents/YM2413ApplicationManual#tableii2) suggests that the delays should be 12cy (A->D) and 84cy (D->A) of the 3.6MHz xtal, or ~3 and 21 NOPs Lidnariq 20:26, 15 May 2012 (PDT)

Yeah, I looked it up afterwards when I realized this info should be in the datasheet. I plan to do some testing of this later to make sure the numbers are good enough; the earlier ballpark guesses were just from trying things until it worked-- I believe some of the registers finish updating faster than others, so my guesses were a bit off from the recommended times, apparently. - Rainwarrior 20:44, 15 May 2012 (PDT)
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