Talk:MMC5: Difference between revisions
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(Add section headers. Also, it's plausible that MMC5 might support up to 1MiB RAM.) |
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== [[wikipedia:Don't repeat yourself|Don't Repeat Yourself]] failure == | |||
Ok, it's crazy to have two completely different pages explaining the MMC5 mapper, one on iNES mapper 5 and the other on MMC5. I think the info should be present on a single page (like it is for all other mappers). | Ok, it's crazy to have two completely different pages explaining the MMC5 mapper, one on iNES mapper 5 and the other on MMC5. I think the info should be present on a single page (like it is for all other mappers). | ||
Well in fact it seems it's Zeromus who added Dish's notes on all iNES mapper pages. This would be nice if the info wasn't already present on the wiki - having twice the same info isn't very logical is it ? I don't know what to do but something should probably be changed...Bregalad 00:36, 23 March 2012 (PDT) | Well in fact it seems it's Zeromus who added Dish's notes on all iNES mapper pages. This would be nice if the info wasn't already present on the wiki - having twice the same info isn't very logical is it ? I don't know what to do but something should probably be changed...Bregalad 00:36, 23 March 2012 (PDT) | ||
Disch' format is '''much''' better for reading. Funny, I was really thinking to discuss about such thing. :) --[[User:Zepper|Zepper]] 14:44, 23 March 2012 (PDT) | :Disch' format is '''much''' better for reading. Funny, I was really thinking to discuss about such thing. :) --[[User:Zepper|Zepper]] 14:44, 23 March 2012 (PDT) | ||
--- | == MMC5-internal RAM == | ||
What is the logic in the ASIC that causes it to write zero if the PPU is not rendering? --[[User:Zzo38|Zzo38]] 01:51, 22 September 2012 (MDT) | |||
== Even more extended PRG RAM == | |||
Parsimony of silicon strongly implies that the higher address lines (corresponding to the 0x78 bits of the register) are still driven for the registers from $5114 to $5116 even when RAM is selected, meaning >64KiB PRG-RAM would be usable when mapped to $8000-$DFFF. | |||
It's conceivable that these same bits of the register at $5113 (controlling PRG-RAM bank) are implemented, since they have to feed a multiplexer anyway. | |||
Something to test, maybe. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 23:34, 20 January 2014 (MST) | |||
Revision as of 06:34, 21 January 2014
Don't Repeat Yourself failure
Ok, it's crazy to have two completely different pages explaining the MMC5 mapper, one on iNES mapper 5 and the other on MMC5. I think the info should be present on a single page (like it is for all other mappers).
Well in fact it seems it's Zeromus who added Dish's notes on all iNES mapper pages. This would be nice if the info wasn't already present on the wiki - having twice the same info isn't very logical is it ? I don't know what to do but something should probably be changed...Bregalad 00:36, 23 March 2012 (PDT)
- Disch' format is much better for reading. Funny, I was really thinking to discuss about such thing. :) --Zepper 14:44, 23 March 2012 (PDT)
MMC5-internal RAM
What is the logic in the ASIC that causes it to write zero if the PPU is not rendering? --Zzo38 01:51, 22 September 2012 (MDT)
Even more extended PRG RAM
Parsimony of silicon strongly implies that the higher address lines (corresponding to the 0x78 bits of the register) are still driven for the registers from $5114 to $5116 even when RAM is selected, meaning >64KiB PRG-RAM would be usable when mapped to $8000-$DFFF. It's conceivable that these same bits of the register at $5113 (controlling PRG-RAM bank) are implemented, since they have to feed a multiplexer anyway. Something to test, maybe. —Lidnariq (talk) 23:34, 20 January 2014 (MST)
