Talk:MMC1 pinout: Difference between revisions
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== SXROM wram == | == SXROM wram == | ||
32K ram does not have an A15 line if the address lines start at the conventional 0, right? pins 9 and 10 should probably be WRAM A13 and A14 respectively? | 32K ram does not have an A15 line if the address lines start at the conventional 0, right? pins 9 and 10 should probably be WRAM A13 and A14 respectively? —[[Special:Contributions/68.107.78.15|68.107.78.15]] ([[User talk:206.174.175.22|talk]]) 19:37, 24 February 2015 (MST) | ||
: Nice catch! Fixed. —[[User:Lidnariq|Lidnariq]] ([[User talk:Lidnariq|talk]]) 21:49, 24 February 2015 (MST) | |||
Revision as of 04:49, 25 February 2015
Tying PA12 low
Based on the description of NES-EVENT (#105), it appears to tie the MMC1's PA12 input low and connect the cart's PA12 to A12 of the CHR RAM. --Tepples 08:31, 12 October 2012 (MDT)
- Given the pictures I can find (kevtris, kevtris-via-bootgod; both are component side only), it looks like the PA12 input is likely still connected to the cartridge edge. I can't tell anything about whether MMC1 CHR A12 OUT goes to CHR RAM A12. And when I load NWC in FCEUX and trap all mapper writes, it looks like the game just uses 8KB mode anyway. —Lidnariq 11:41, 12 October 2012 (MDT)
SNROM, etc... loses CHR banking ?
I'm pretty sure they don't, they just bank only 8k as they were always supposed to, and it's possible to have two banks of 4k and bankswitch them independently. I might be wrong, I'll have to double check. Bregalad (talk) 04:26, 15 May 2014 (MDT)
SXROM wram
32K ram does not have an A15 line if the address lines start at the conventional 0, right? pins 9 and 10 should probably be WRAM A13 and A14 respectively? —68.107.78.15 (talk) 19:37, 24 February 2015 (MST)
