VRC6 pinout: Difference between revisions
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Konami [[VRC6]]: 48-pin 0.6" PDIP marked "053328 VRC VI" or "053329 VRC VI" (iNES Mappers [[iNES Mapper 024|24]] and [[iNES Mapper 026|26]]) | |||
.---\/---. | |||
- | ?GND -> | 01 48 | -- +5V | ||
AUD D1 <- | 02 47 | -> AUD D0 | |||
( | AUD D3 <- | 03 46 | -> AUD D2 | ||
AUD D5 <- | 04 45 | -> AUD D4 | |||
(fr) CPU A12 -> | 05 44 | -> PRG A16 (r) | |||
(f) CPU A14 -> | 06 43 | <- CPU A13 (f) | |||
(f) M2 -> | 07 42 | -> PRG A17 (r) | |||
(r) PRG A14 <- | 08 41 | -> PRG A15 (r) | |||
(fr) CPU A1 -> | 09 40 | -> PRG A13 (r) | |||
(fr) CPU A0 -> | 10 39 | <- CPU D7 (fr) | |||
(fr) CPU D0 -> | 11 38 | <- CPU D6 (fr) | |||
(fr) CPU D1 -> | 12 37 | <- CPU D5 (fr) | |||
(fr) CPU D2 -> | 13 36 | <- CPU D4 (fr) | |||
(r) PRG /CE <- | 14 35 | <- CPU D3 (fr) | |||
(f) R/W -> | 15 34 | <- /ROMSEL (f) | |||
WRAM /CE <- | 16 33 | -> /IRQ (f) | |||
(r) CHR /CE <- | 17 32 | -> CIRAM /CE (f) | |||
(f) PPU /RD -> | 18 31 | <- PPU A10 (f) | |||
(f) PPU /A13 -> | 19 30 | <- PPU A11 (f) | |||
(r) CHR A16 <- | 20 29 | <- PPU A12 (f) | |||
(r) CHR A15 <- | 21 28 | -> CHR A17 (r) | |||
(r) CHR A12 <- | 22 27 | -> CHR A14 (r) | |||
(r) CHR A11 <- | 23 26 | -> CHR A13 (r) | |||
GND -- | 24 25 | -> CHR A10 (r) | |||
`--------' | |||
1: conceivably an input instead of a power supply? | |||
2-4, 45-47: goes to a 6 bit DAC, and then mixed with system audio | |||
9,10: Swapped between m24 (VRC6a) and m26 (VRC6b), but which is which is not known | |||
16: passes through a small pulse-shaping network consisting of a resistor, diode, and capacitor. | |||
32: This is odd: this would only be useful if the VRC6 supported ROM nametables. | |||
Revision as of 23:55, 29 January 2013
Konami VRC6: 48-pin 0.6" PDIP marked "053328 VRC VI" or "053329 VRC VI" (iNES Mappers 24 and 26)
.---\/---. ?GND -> | 01 48 | -- +5V AUD D1 <- | 02 47 | -> AUD D0 AUD D3 <- | 03 46 | -> AUD D2 AUD D5 <- | 04 45 | -> AUD D4 (fr) CPU A12 -> | 05 44 | -> PRG A16 (r) (f) CPU A14 -> | 06 43 | <- CPU A13 (f) (f) M2 -> | 07 42 | -> PRG A17 (r) (r) PRG A14 <- | 08 41 | -> PRG A15 (r) (fr) CPU A1 -> | 09 40 | -> PRG A13 (r) (fr) CPU A0 -> | 10 39 | <- CPU D7 (fr) (fr) CPU D0 -> | 11 38 | <- CPU D6 (fr) (fr) CPU D1 -> | 12 37 | <- CPU D5 (fr) (fr) CPU D2 -> | 13 36 | <- CPU D4 (fr) (r) PRG /CE <- | 14 35 | <- CPU D3 (fr) (f) R/W -> | 15 34 | <- /ROMSEL (f) WRAM /CE <- | 16 33 | -> /IRQ (f) (r) CHR /CE <- | 17 32 | -> CIRAM /CE (f) (f) PPU /RD -> | 18 31 | <- PPU A10 (f) (f) PPU /A13 -> | 19 30 | <- PPU A11 (f) (r) CHR A16 <- | 20 29 | <- PPU A12 (f) (r) CHR A15 <- | 21 28 | -> CHR A17 (r) (r) CHR A12 <- | 22 27 | -> CHR A14 (r) (r) CHR A11 <- | 23 26 | -> CHR A13 (r) GND -- | 24 25 | -> CHR A10 (r) `--------' 1: conceivably an input instead of a power supply? 2-4, 45-47: goes to a 6 bit DAC, and then mixed with system audio 9,10: Swapped between m24 (VRC6a) and m26 (VRC6b), but which is which is not known 16: passes through a small pulse-shaping network consisting of a resistor, diode, and capacitor. 32: This is odd: this would only be useful if the VRC6 supported ROM nametables.