VRC6: Difference between revisions

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(First draft of explaining $b003 register. A few odd bits remain to be explained.)
(→‎PPU Banking Style ($B003): bootgod did some tests. The VRC6's extended modes are kinda daft.)
Line 44: Line 44:
  | || ||||
  | || ||||
  | || ||++- PPU addressing mode; see below
  | || ||++- PPU addressing mode; see below
  | || ++--- [[Mirroring]] (0: vertical; 1: horizontal;
  | || ++--- [[Mirroring]] varies by addressing mode, see below
| ||                      2: one-screen, lower bank; 3: one-screen, upper bank)
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | +------- 1: Pattern tables come from CHRROM, (0: buggy)
  | +------- CHR A10 is 1: subject to further rules 0: according to the latched value
  +--------- PRG RAM enable
  +--------- PRG RAM enable


In practice, all VRC6 games used the Famicom's CIRAM as the CHRRAM, like the [[Namco 163]]. A game could have been made that used a separate larger CHRRAM instead.
The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM.


==== Nametable control in mode 0 ====
==== Nametable control in mode 0 ====
CHRRAM A10 is connected according to the mirroring control bits.
If the $20s bit is set, CHR A10 is connected according to the $04s and $08s bits as follows:
{| class="wikitable"
| 0 || vertical mirroring || CHR A10 = PPU A10
|-
| 4 || horizontal mirroring || CHR A10 = PPU A11
|-
| 8 || one-screen lower || CHR A10 = ground
|-
| 12 || one-screen upper || CHR A10 = vcc
|}
 
The upper address lines, regardless of whether the $20s bit is set, are filled with the values of CHR select 6 and 7. They are laid out according to the $04s bit:
{| class="wikitable"
| 0 || vertical ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
|-
| 4 || horizontal ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
|}
 
If the $20s bit is clear, CHR A10 follows the rest of the address lines.


It is not known what the MSBs of nametable registers are.
==== Nametable control in mode 1 ====
==== Nametable control in mode 1 ====
The values written to $E00x specify the banks used for nametables.
The values written to CHRSEL[4…7] specify the banks used for nametables, without further modification.
 
For the 2KiB pattern table banks,
if the $20s bit is set, CHR A10 = PPU A10.
If the $20s bit is clear, CHR A10 parallels all the upper bits in CHRSEL[0…3]. It is then assumed that PPU A10 is connected to CHRROM separately.
 
The $04s and $08s bits are ignored.


==== Nametable control in mode 2 ====
==== Nametable control in mode 2 ====
The value written to $E002 specifies the bank used in lieu of CIRAM $000-$3FF.
The value written to CHRSEL[6] specifies the bank used in lieu of CIRAM $000-$3FF.
The value written to $E003 specifies the bank used in lieu of CIRAM $400-$7FF.
The value written to CHRSEL[7] specifies the bank used in lieu of CIRAM $400-$7FF.
These are then placed into the nametables according to the mirroring control bits.
 
These are then placed into the nametables according to the $04s bit, using the opposite table as mode 0:
{| class="wikitable"
| 0 || horizontal ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
|-
| 4 || vertical ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
|}
 
These are then placed into the nametables according to the $04s bit, using the same table as mode 0.
 
The $20s bit only affects the two pattern table banks, using the same rule as given for mode 1.
 
The only way to get one-screen mirroring is by writing the same value to both CHRSEL[6] and [7].
 
The $08s bit is ignored.


This behavior is identical to the [[iNES Mapper 068|Sunsoft 4]] mapper.
This behavior is identical to the [[iNES Mapper 068|Sunsoft 4]] mapper.


==== Nametable control in mode 3 ====
==== Nametable control in mode 3 ====
CHRRAM A10 is connected according to the mirroring control bits. For both
Mode 3 is identical to mode 2, except that the $08s and $20s bits affect the nametables:
registers mentioned below, the LSB is ignored (and pays attention to the
mirroring control bits instead)


The value written to $E002 specifies a 2 KiB bank to be used for the left or top two nametables.
If the $20s bit is clear, mode 3 is identical to mode 2.
The value written to $E003 specifies a 2 KiB bank to be used for the right or bottom two nametables.


The mirroring bits specify whether it's side-by-side or top-and-bottom:
If the $20s bit is set, CHR A10 is instead connected according to the $04s and $08s bits:
Mirroring = 0, 8 - left and right
{| class="wikitable"
          = 4, C - top and bottom
| 0 || horizontal mirroring || CHR A10 = PPU A11
|-
| 4 || vertical mirroring || CHR A10 = PPU A10
|-
| 8 || one-screen upper || CHR A10 = vcc
|-
| 12 || one-screen lower || CHR A10 = gnd
|}
This is the same as the table in mode 0, but with the $04s bit inverted.


=== CHR Select 0…7 ($Dxxx, $Exxx) ===
=== CHR Select 0…7 ($Dxxx, $Exxx) ===

Revision as of 08:46, 12 November 2013

The Konami's VRC6 ASIC mapper comes in two variants. The register descriptions given here are as they exist in Akumajou Densetsu (iNES Mapper 024). The A0 and A1 lines are switched in Madara and Esper Dream 2 (iNES Mapper 026), so for those games, adjustments will need to be made ($x001 becomes $x002 and vice versa).



Overview

  • PRG ROM size: Up to 256 KB
  • PRG ROM bank size: 16 KB at $8000, 8 KB at $C000
  • PRG RAM: Up to 8 KB
  • CHR capacity: Up to 256 KB ROM
  • CHR bank size: 1 KB
  • Nametable mirroring: Controlled by mapper
  • Subject to bus conflicts: No

See VRC6 pinout for chip pinout.

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM at $C000

PPU Banking Style ($B003)

7  bit  0
---------
W.PN MMDD
| || ||||
| || ||++- PPU addressing mode; see below
| || ++--- Mirroring varies by addressing mode, see below
| |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
| +------- CHR A10 is 1: subject to further rules 0: according to the latched value
+--------- PRG RAM enable

The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM.

Nametable control in mode 0

If the $20s bit is set, CHR A10 is connected according to the $04s and $08s bits as follows:

0 vertical mirroring CHR A10 = PPU A10
4 horizontal mirroring CHR A10 = PPU A11
8 one-screen lower CHR A10 = ground
12 one-screen upper CHR A10 = vcc

The upper address lines, regardless of whether the $20s bit is set, are filled with the values of CHR select 6 and 7. They are laid out according to the $04s bit:

0 vertical layout CHR A11…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
4 horizontal layout CHR A11…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])

If the $20s bit is clear, CHR A10 follows the rest of the address lines.

Nametable control in mode 1

The values written to CHRSEL[4…7] specify the banks used for nametables, without further modification.

For the 2KiB pattern table banks, if the $20s bit is set, CHR A10 = PPU A10. If the $20s bit is clear, CHR A10 parallels all the upper bits in CHRSEL[0…3]. It is then assumed that PPU A10 is connected to CHRROM separately.

The $04s and $08s bits are ignored.

Nametable control in mode 2

The value written to CHRSEL[6] specifies the bank used in lieu of CIRAM $000-$3FF. The value written to CHRSEL[7] specifies the bank used in lieu of CIRAM $400-$7FF.

These are then placed into the nametables according to the $04s bit, using the opposite table as mode 0:

0 horizontal layout CHR A10…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
4 vertical layout CHR A10…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])

These are then placed into the nametables according to the $04s bit, using the same table as mode 0.

The $20s bit only affects the two pattern table banks, using the same rule as given for mode 1.

The only way to get one-screen mirroring is by writing the same value to both CHRSEL[6] and [7].

The $08s bit is ignored.

This behavior is identical to the Sunsoft 4 mapper.

Nametable control in mode 3

Mode 3 is identical to mode 2, except that the $08s and $20s bits affect the nametables:

If the $20s bit is clear, mode 3 is identical to mode 2.

If the $20s bit is set, CHR A10 is instead connected according to the $04s and $08s bits:

0 horizontal mirroring CHR A10 = PPU A11
4 vertical mirroring CHR A10 = PPU A10
8 one-screen upper CHR A10 = vcc
12 one-screen lower CHR A10 = gnd

This is the same as the table in mode 0, but with the $04s bit inverted.

CHR Select 0…7 ($Dxxx, $Exxx)

PPU addressing mode 0 1 2 or 3
Write to CPU address CHR banks affected
$D000 $0000-$03FF $0000-$07FF $0000-$03FF
$D001 $0400-$07FF $0800-$0FFF $0400-$07FF
$D002 $0800-$0BFF $1000-$17FF $0800-$0BFF
$D003 $0C00-$0FFF $1800-$1FFF $0C00-$0FFF
$E000 $1000-$13FF $2000-$23FF $1000-$17FF
$E001 $1400-$17FF $2400-$27FF $1800-$1FFF
$E002 $1800-$1BFF $2800-$2BFF see previous
$E003 $1C00-$1FFF $2C00-$2FFF see previous

2KiB slices always ignore the LSB, like the MMC3 does.

IRQ control ($F00x)

$F000:  IRQ Latch
$F001:  IRQ Control
$F002:  IRQ Acknowledge

Many VRC mappers use the same IRQ system. For details on IRQ operation, see VRC IRQs.

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.

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