PRG RAM circuit: Difference between revisions

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(So it is the Family BASIC circuit)
(Removed older circuit suggestions)
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== kyuusaku's circuit ==
== kyuusaku's circuit ==
On the forum, kyuusaku has suggested an SRAM decoder circuit[http://nesdev.parodius.com/bbs/viewtopic.php?p=32389#32389] to approximate this behavior in an NES cartridge board.
On the forum, kyuusaku and Bregalad discussed SRAM decoder circuits built from [[wikipedia:List of 7400 series integrated circuits|7400 series parts]] to approximate this behavior in an NES cartridge board.
It can be built from [[wikipedia:List of 7400 series integrated circuits|7400 series parts]]: a 74HC00 (4 NANDs) and a 74HC04 (6 inverters), or from two 74HC00s (because a NAND with both inputs equal acts as an inverter).
The first tries took two chips[http://nesdev.parodius.com/bbs/viewtopic.php?p=32389#32389] or had possible timing problems.[http://nesdev.parodius.com/bbs/viewtopic.php?p=32520#32520][http://nesdev.parodius.com/bbs/viewtopic.php?p=32531#32531] They settled on the following circuits:
<pre>
NES cart edge                    SRAM chip
                      ___
R/W ----+-------------|  `.
        |            |    )o--------- /OE
Phi2 ---(----------+--|___,'
        |          |
        |          |  ___
        |          `--|  `.
        |  |`.        |    )o--------- /WE
        `--|  >o------|___,'
          |,'
 
          ___
/ROMSEL --|  `.   |`.       ___
          |    )o--|  >o----|  `.
A14 ------|___,'    |,'      |    )o-- /CE
                          ,--|___,'
A13 ---------------------'
</pre>
kyuusaku also pointed out that a 74HC138 or 74HC139 can decode the address using one spare inverter, leaving the details as an exercise for the reader.
 
== Bregalad's circuit ==
Bregalad suggested an even simpler circuit using one 74HC08, 74HC20, or 74HC21 chip, which exploits the 6264 SRAM's /WE behavior:[http://nesdev.parodius.com/bbs/viewtopic.php?p=32520#32520]
:AND A13, A14, /ROMSEL and PHI2 together (it shouldn't matter in which order) and feed the output to positive chip enable pin, ground the negative chip enable pin and connect /WE to R/W and /OE to ground and that should to it.
One side of a 74HC21 (dual 4-input AND) or 74HC20 (dual 4-input NAND) could compute the same function.
 
== kyuusaku's second circuit ==
kyuusaku found potential timing problems with Bregalad's circuit and suggested a refinement of his own circuit based on a 7410 (triple 3-input NAND):[http://nesdev.parodius.com/bbs/viewtopic.php?p=32531#32531]
<pre>
NES cart edge                  RAM
 
              ____
/ROMSEL -----|    `-.
            |      \
A14 ---------|        )o------ /CS
            |      /
A13 ---------|____,-'
 
              ____
R/W ---------|    `-.
            |      \
Phi2 -----+--|        )o--+--- /OE
          |  |      /    |
          +--|____,-'    |
          |              |
          |  ____        |
          +--|    `-.    |
          |  |      \    |
          +--|        )o--(--- /WE
            |      /    |
          ,--|____,-'    |
          |              |
          `---------------'
</pre>
On each of the NANDs that produce /OE and /WE, one Phi2 input can be replaced with Vdd (constant +5 V) if it simplifies routing.


== More suggestions from kyuusaku ==
== Using 7410 ==


kyuusaku found "a race condition that could trigger unintentional writes" in the second circuit. Then he figured how to stick a pulldown on CE2 to take advantage of Phi2 going high-impedance during reset in order to "offer some write protection".[http://nesdev.parodius.com/bbs/viewtopic.php?p=35231#35231]
kyuusaku suggested a circuit based on a 74HC10 (triple three-input NAND) stick a pulldown on CE2 to take advantage of Phi2 going high-impedance during reset in order to "offer some write protection".[http://nesdev.parodius.com/bbs/viewtopic.php?p=35231#35231]
<pre>
<pre>
           ,-------------- ROM /CE
           ,-------------- ROM /CE
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</pre>
</pre>


== Using 7420 ==
He also suggested a circuit based on a 74HC20 (double 4-input NAND), which appears to be the same one in ''Family BASIC'':
He also suggested a circuit based on a 74HC20 (double 4-input NAND), which appears to be the same one in ''Family BASIC'':
:Or you could just use a NAND4 to decode any active low memory, also using the /WE priority method. If this is done with a two gate 7420, the second gate could be used to invert r/w to prevent bus conflicts as in the circuit above. This is probably the *final* best way unless you happen to need the extra AND3 from the 7410 and have a positive CE.
:Or you could just use a NAND4 to decode any active low memory, also using the /WE priority method. If this is done with a two gate 7420, the second gate could be used to invert r/w to prevent bus conflicts as in the circuit above. This is probably the *final* best way unless you happen to need the extra AND3 from the 7410 and have a positive CE.

Revision as of 19:26, 23 February 2011

The iNES format implies 8 KiB of PRG RAM at $6000-$7FFF, which may or may not be battery backed, even for discrete boards such as NROM and UxROM that never actually had SRAM there. This inspired some people on the nesdev.org BBS to come up with circuits to add PRG RAM to the original boards, so that games relying on it can run on an NES.

Some gotchas to watch out for include the fact that PRG /CE and M2, used together to decode $6000-$7FFF, don't change at the same time. Writes to a mapper register at $E000-$FFFF can cause spurious writes to PRG RAM, as pointed out by loopy.

kyuusaku's circuit

On the forum, kyuusaku and Bregalad discussed SRAM decoder circuits built from 7400 series parts to approximate this behavior in an NES cartridge board. The first tries took two chips[1] or had possible timing problems.[2][3] They settled on the following circuits:

Using 7410

kyuusaku suggested a circuit based on a 74HC10 (triple three-input NAND) stick a pulldown on CE2 to take advantage of Phi2 going high-impedance during reset in order to "offer some write protection".[4] 

           ,-------------- ROM /CE
          |   ____
/ROMSEL --+--|    `-.
             |       \
A14 ---------|        )o-- RAM /CE
             |       /
A13 ---------|____,-'

              ____
+5V ------+--|    `-.
          |  |       \
          `--|        )o-- ROM /OE
             |       /
R/W ------+--|____,-'
          |
          `--------------- RAM /WE

Phi2 ---------+----------- RAM CE2
              |
              <
              < "big R"
              <
              |
GND ----------+----------- RAM /OE

Using 7420

He also suggested a circuit based on a 74HC20 (double 4-input NAND), which appears to be the same one in Family BASIC:

Or you could just use a NAND4 to decode any active low memory, also using the /WE priority method. If this is done with a two gate 7420, the second gate could be used to invert r/w to prevent bus conflicts as in the circuit above. This is probably the *final* best way unless you happen to need the extra AND3 from the 7410 and have a positive CE.

The pinout:

  • A = Phi2
  • B = /ROMSEL
  • C = A14
  • D = A13
  • Y = WRAM /CE
  • WRAM /OE = GND
  • WRAM /WE = Vcc or R//W, depending on the Family BASIC cart's write-protect switch

You could also use the other gate to invert R//W and use that for /OE (for /OE on the ROM too to prevent bus conflicts).

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