BNROM: Difference between revisions
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{{Infobox_iNES_mapper | |||
|name=BNROM | |||
|company=Irem, Nintendo | |||
|mapper=34 | |||
|nescartdbgames=2 | |||
|othermappers=[[iNES Mapper 241|241]], [[iNES Mapper 177|177]] | |||
|complexity=Discrete logic | |||
|boards=I-IM, BNROM | |||
|prgmax=128K | |||
|prgpage=32K | |||
|chrmax=8K | |||
|chrpage=n/a | |||
|busconflicts=Yes | |||
}} | |||
{{nesdbbox | |||
|ines|34|iNES 034 | |||
|unif_wild|BNROM|BNROM | |||
}} | |||
[[Category:Mappers with CHR RAM]][[Category:Mappers with bus conflicts]][[Category:Discrete logic mappers]][[Category:Nintendo licensed mappers]][[Category:NES 2.0 mappers with submappers]] | |||
The designation BNROM refers to the Irem cartridge board "Irem I-IM" and to its NES workalike, the Nintendo cartridge board NES-BNROM. These boards were used only for one licensed game: ''Deadly Towers'' (Japanese ''Mashou''). An unlicensed game, ''Journey to the West'', runs on a functionally equivalent circuit board. (Its commonly-available ROM image file is a hacked version that no longer works as BNROM due to bus conflicts). The [[iNES]] format assigns [[iNES Mapper 034|mapper 34]] to BNROM (as well as [[NINA-001]]). | |||
== Overview == | == Overview == | ||
* PRG ROM size: 128 KB ( | * PRG ROM size: 128 KB (mapper implementations may support up to 512 KB or 8 MB) | ||
* PRG ROM bank size: 32 KB | * PRG ROM bank size: 32 KB | ||
* PRG RAM: None | * PRG RAM: None | ||
* CHR capacity: 8 KB RAM | * CHR capacity: 8 KB RAM | ||
* CHR bank size: Not bankswitched | * CHR bank size: Not bankswitched | ||
* Nametable [[mirroring]]: Solder pads select vertical or horizontal mirroring | * Nametable [[mirroring]]: Solder pads select vertical or horizontal mirroring | ||
* Subject to [[bus conflict]]s: Yes | * Subject to [[bus conflict]]s: Yes | ||
The bank number at power on is not defined. | Notes: | ||
The 6502's vectors must be present in all banks, along with the NMI, reset, and IRQ handlers. | * BNROM PRG uses the DIP-28 Nintendo pinout. | ||
* The bank number at power on is not defined. | |||
* The 6502's vectors must be present in all banks, along with the NMI, reset, and IRQ handlers. | |||
* [[iNES Mapper 034]] implementations frequently support either a 4-bit or 8-bit PRG bank select register, allowing up to 512 KB or 8 MB of PRG ROM. This variant may be referred to as '''BxROM'''. | |||
== Banks == | == Banks == | ||
| Line 27: | Line 49: | ||
|| | || | ||
++- Select 32 KB PRG ROM bank for CPU $8000-$FFFF | ++- Select 32 KB PRG ROM bank for CPU $8000-$FFFF | ||
While the original BNROM board connects only 2 bits, it is recommended that emulators implement this as an 8-bit register allowing selection of up to 8 MB PRG ROM if present. | |||
== Hardware == | == Hardware == | ||
The | The BNROM board contains a [[74161|74HC161]] binary counter used as a quad D latch (4-bit register) to select the current PRG bank. | ||
== Variants == | == Variants == | ||
The | [[AxROM|AMROM]] is the same as BNROM except it uses bit 4 of the register to control a single screen mirroring configuration, instead of fixed mirroring. | ||
The upper 2 bank select bits on the 74HC161 were left unconnected. These bits could have been used for an [[oversize]] variant of BNROM supporting up to 512 KB (4 Mbit) of PRG ROM. Some emulators support this oversize variation, as well as the [[PowerPak]] since a [http://forums.nesdev.org/viewtopic.php?p=79826#p79826 mapper update in June 2011]. | |||
Theoretically the bank select register could be implemented with a [[74377|74HC377]] octal latch, allowing up to 8 MB of PRG ROM. | |||
The | The ''[[Action 53]]'' multicart used the BxROM oversize extension before [[iNES Mapper 028|mapper 28]] was developed. | ||
[[INES Mapper 241]] describes a BxROM circuit board with 8 KiB of WRAM at CPU $6000-$7FFF; [[INES Mapper 177]] adds a bit for mapper-controlled two-screen mirroring. | |||
[[ | == iNES mapper 034 and NINA-001 == | ||
The iNES mapper used to implement this mapper also includes three additional registers at $7FFD-$7FFF for emulation of the [[NINA-001]] board (using CHR ROM instead of RAM, as well as supporting 8KB of PRG RAM), which has caused many headaches for NES emulator authors. Emulator developers may consider switching between NINA-001 emulation and BxROM emulation based on the presence of CHR ROM. [[NES 2.0 submappers#034: 2 BNROM|NES 2.0 submapper 034:2]] can be used to specify BNROM behavior. | |||
Latest revision as of 08:25, 10 January 2024
| Company | Irem, Nintendo |
| Games | 2 in NesCartDB |
| Complexity | Discrete logic |
| Boards | I-IM, BNROM |
| PRG ROM capacity | 128K |
| PRG ROM window | 32K |
| PRG RAM capacity | None |
| CHR capacity | 8K |
| CHR window | n/a |
| Nametable mirroring | Fixed H or V, controlled by solder pads |
| Bus conflicts | Yes |
| IRQ | No |
| Audio | No |
| iNES mappers | 034, 241, 177 |
The designation BNROM refers to the Irem cartridge board "Irem I-IM" and to its NES workalike, the Nintendo cartridge board NES-BNROM. These boards were used only for one licensed game: Deadly Towers (Japanese Mashou). An unlicensed game, Journey to the West, runs on a functionally equivalent circuit board. (Its commonly-available ROM image file is a hacked version that no longer works as BNROM due to bus conflicts). The iNES format assigns mapper 34 to BNROM (as well as NINA-001).
Overview
- PRG ROM size: 128 KB (mapper implementations may support up to 512 KB or 8 MB)
- PRG ROM bank size: 32 KB
- PRG RAM: None
- CHR capacity: 8 KB RAM
- CHR bank size: Not bankswitched
- Nametable mirroring: Solder pads select vertical or horizontal mirroring
- Subject to bus conflicts: Yes
Notes:
- BNROM PRG uses the DIP-28 Nintendo pinout.
- The bank number at power on is not defined.
- The 6502's vectors must be present in all banks, along with the NMI, reset, and IRQ handlers.
- iNES Mapper 034 implementations frequently support either a 4-bit or 8-bit PRG bank select register, allowing up to 512 KB or 8 MB of PRG ROM. This variant may be referred to as BxROM.
Banks
- CPU $8000-$FFFF: 32 KB switchable PRG ROM bank
Solder pad config
- Horizontal mirroring : 'H' disconnected, 'V' connected.
- Vertical mirroring : 'H' connected, 'V' disconnected.
Registers
Bank select ($8000-$FFFF)
7 bit 0
---- ----
xxxx xxPP
||
++- Select 32 KB PRG ROM bank for CPU $8000-$FFFF
While the original BNROM board connects only 2 bits, it is recommended that emulators implement this as an 8-bit register allowing selection of up to 8 MB PRG ROM if present.
Hardware
The BNROM board contains a 74HC161 binary counter used as a quad D latch (4-bit register) to select the current PRG bank.
Variants
AMROM is the same as BNROM except it uses bit 4 of the register to control a single screen mirroring configuration, instead of fixed mirroring.
The upper 2 bank select bits on the 74HC161 were left unconnected. These bits could have been used for an oversize variant of BNROM supporting up to 512 KB (4 Mbit) of PRG ROM. Some emulators support this oversize variation, as well as the PowerPak since a mapper update in June 2011.
Theoretically the bank select register could be implemented with a 74HC377 octal latch, allowing up to 8 MB of PRG ROM.
The Action 53 multicart used the BxROM oversize extension before mapper 28 was developed.
INES Mapper 241 describes a BxROM circuit board with 8 KiB of WRAM at CPU $6000-$7FFF; INES Mapper 177 adds a bit for mapper-controlled two-screen mirroring.
iNES mapper 034 and NINA-001
The iNES mapper used to implement this mapper also includes three additional registers at $7FFD-$7FFF for emulation of the NINA-001 board (using CHR ROM instead of RAM, as well as supporting 8KB of PRG RAM), which has caused many headaches for NES emulator authors. Emulator developers may consider switching between NINA-001 emulation and BxROM emulation based on the presence of CHR ROM. NES 2.0 submapper 034:2 can be used to specify BNROM behavior.
