NES 2.0 Mapper 548: Difference between revisions
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NewRisingSun (talk | contribs) (Created page with "{{DEFAULTSORT:304}}Category:FDS conversion mappersCategory:Mappers with fixed-timing cycle IRQsCategory:Mappers with CHR RAM '''NES 2.0 Mapper 548''' denotes 科...") |
(→Latch and IRQ control ($4800, write): (typo) + pedantry about IRQ counter) |
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{{DEFAULTSORT: | {{DEFAULTSORT:548}}[[Category:FDS conversion mappers]][[Category:Mappers with fixed-timing cycle IRQs]][[Category:Mappers with CHR RAM]] | ||
'''NES 2.0 Mapper 548''' denotes 科統實業股份有限公司 (Co Tung Co.)'s '''CTC-15''' circuit board, used for their cartridge conversion of the FDS game ''Almanaの奇跡 (Almana no Kiseki)''. | '''NES 2.0 Mapper 548''' denotes 科統實業股份有限公司 (Co Tung Co.)'s '''CTC-15''' circuit board, used for their cartridge conversion of the FDS game ''Almanaの奇跡 (Almana no Kiseki)''. | ||
=Banks= | =Banks= | ||
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Power-on value (ABC): $7 | Power-on value (ABC): $7 | ||
* The latch value is not used until the Latch Apply register is | * The latch value is not used until the Latch Apply register is written to. | ||
* IRQ control: | * IRQ control: | ||
** 0: Enable M2 counting and IRQ generation | ** 0: Enable M2 counting and IRQ generation | ||
** 1: Disable M2 counting and IRQ generation, acknowledge IRQ. | ** 1: Disable M2 counting and IRQ generation, acknowledge IRQ, counter is reset to 0. | ||
If counting is enabled, the counter is clocked on every falling edge of M2. | If counting is enabled, the counter is clocked on every falling edge of M2. IRQ is asserted while <tt>((counter÷640)&37)=37</tt>, so it is asserted the first time when the counter reaches 23680 and self-acknowledges the first time when it reaches 24320. | ||
==Latch Apply ($5000, write)== | ==Latch Apply ($5000, write)== | ||
Mask: $F800 | Mask: $F800 | ||
Latest revision as of 19:35, 9 October 2019
NES 2.0 Mapper 548 denotes 科統實業股份有限公司 (Co Tung Co.)'s CTC-15 circuit board, used for their cartridge conversion of the FDS game Almanaの奇跡 (Almana no Kiseki).
Banks
- CPU $6000-$7FFF: 8 KiB unbanked PRG-RAM
- CPU $8000-$BFFF: Switchable 16 KiB PRG-ROM bank
- CPU $C000-$FFFF: Fixed 16 KiB PRG-ROM bank #3
- PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM
Mirroring is hard-wired to Horizontal.
Registers
Latch and IRQ control ($4800, write)
Mask: $F800
A~FEDC BA98 7654 3210
-------------------
0100 1... ..A. BC..
+--++--- Latch value
+--- IRQ control
Power-on value (ABC): $7
- The latch value is not used until the Latch Apply register is written to.
- IRQ control:
- 0: Enable M2 counting and IRQ generation
- 1: Disable M2 counting and IRQ generation, acknowledge IRQ, counter is reset to 0.
If counting is enabled, the counter is clocked on every falling edge of M2. IRQ is asserted while ((counter÷640)&37)=37, so it is asserted the first time when the counter reaches 23680 and self-acknowledges the first time when it reaches 24320.
Latch Apply ($5000, write)
Mask: $F800
Upon writing to the $5000-$57FF address range, the latched value written to $4800 is XOR'd with $05 and applied as the 16 KiB PRG-ROM bank at CPU $8000-$BFFF. The power-on bank is $7.
