NES 2.0 Mapper 336: Difference between revisions
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{{DEFAULTSORT:336}}[[Category:Multicart mappers]][[Category:Mappers with CHR RAM]] | {{DEFAULTSORT:336}}[[Category:Multicart mappers]][[Category:Mappers with CHR RAM]] | ||
NES 2.0 mapper 336 is used for | '''NES 2.0 mapper 336''' is used for multicarts containing several UNROM games. Its UNIF board name is '''BMC-K-3046'''. | ||
'''Submapper 0:''' | |||
* 11-in-1 (K-3046) | |||
* 2-in-1 (YH-217) | |||
* 4-in-1 (YH-4109) | |||
'''Submapper 1 (M1K30 PCB):''' | |||
* Top Gun III 2-in-1 | |||
'''Submapper 2:''' | |||
* 2-in-1 (YH-218) | |||
=Banks= | =Banks= | ||
| Line 15: | Line 24: | ||
|| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF | || |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF | ||
++-+---- Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF | ++-+---- Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF | ||
| +---- Mirroring ('''Submapper 2'''), 1=H, 0=V | |||
+------- Mirroring ('''Submappers 0/1'''), 1=H, 0=V | |||
==Note== | ==Note== | ||
'''Submappers 0''' and '''2''' have no bus conflicts. '''Submapper 1''' does: D0-D2 are affected by normal AND-type bus conflicts, while D3 has a resistor in the signal path to ensure that the ROM bit always "wins", similar to [[INES Mapper 144]]. This behavior is necessary for proper function. | |||
Latest revision as of 16:19, 6 June 2024
NES 2.0 mapper 336 is used for multicarts containing several UNROM games. Its UNIF board name is BMC-K-3046.
Submapper 0:
- 11-in-1 (K-3046)
- 2-in-1 (YH-217)
- 4-in-1 (YH-4109)
Submapper 1 (M1K30 PCB):
- Top Gun III 2-in-1
Submapper 2:
- 2-in-1 (YH-218)
Banks
- CPU $8000-$BFFF: Switchable 16 KiB inner PRG-ROM bank and switchable 128 KiB outer PRG-ROM bank
- CPU $C000-$FFFF: Fixed 16 KiB inner PRG-ROM bank #7 and switchable 128 KiB outer PRG-ROM bank
- PPU $0000-$1FFF: Unbanked 8 KiB CHR-RAM
Data Latch ($C000-$FFFF)
Mask: $8000
D~7654 3210
---------
..OO OIII
|| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF
++-+---- Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF
| +---- Mirroring (Submapper 2), 1=H, 0=V
+------- Mirroring (Submappers 0/1), 1=H, 0=V
Note
Submappers 0 and 2 have no bus conflicts. Submapper 1 does: D0-D2 are affected by normal AND-type bus conflicts, while D3 has a resistor in the signal path to ensure that the ROM bit always "wins", similar to INES Mapper 144. This behavior is necessary for proper function.
