MMC4: Difference between revisions
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[[Category: | {{Infobox iNES mapper | ||
|name=MMC4 | |||
|name2=FxROM | |||
|company=Nintendo | |||
|mapper=10 | |||
|nescartdbgames=3 | |||
|complexity=ASIC | |||
|boards=FJROM, FKROM | |||
|pinout=MMC4 pinout | |||
|prgmax=256K | |||
|prgpage=16K + 16K fixed | |||
|wrammax=8K | |||
|wrampage=8K | |||
|chrmax=128K | |||
|chrpage=4K + 4K (triggered) | |||
|mirroring=H or V, switchable | |||
|busconflicts=No | |||
}} | |||
[[Category:Nintendo licensed mappers]] [[Category:Mappers triggering on reads]] | |||
The '''Nintendo MMC4''' is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]], used on the [[FxROM]] board set. The [[iNES]] format assigns '''mapper 10''' to these boards. The chip first appeared in August 1988. | The '''Nintendo MMC4''' is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]], used on the [[FxROM]] board set. The [[iNES]] format assigns '''mapper 10''' to these boards. The chip first appeared in August 1988. | ||
Nintendo's MMC2, used in PxROM boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left (low) pattern table. This page only explains the differences, see [[MMC2]] for full details on the rest of the mapper. | |||
== Banks == | == Banks == | ||
| Line 18: | Line 29: | ||
* PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks | * PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks | ||
When the PPU reads from specific tiles in the pattern table during rendering, the MMC4 sets a latch that tells it to use a different 4 KB bank number. | When the PPU reads from specific tiles in the pattern table during rendering, the MMC4 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolising the CPU. | ||
*PPU reads $ | |||
*PPU reads $ | *PPU reads $0FD8 through $0FDF: latch 0 is set to $FD | ||
*PPU reads $ | *PPU reads $0FE8 through $0FEF: latch 0 is set to $FE | ||
*PPU reads $ | *PPU reads $1FD8 through $1FDF: latch 1 is set to $FD | ||
*PPU reads $1FE8 through $1FEF: latch 1 is set to $FE | |||
== Registers == | == Registers == | ||
The MMC4 has 6 registers at $A000-$AFFF, $B000-$BFFF, $C000-$CFFF, $D000-$DFFF, $E000-$EFFF and $F000-$FFFF. Only $A000-$AFFF is covered here. For the rest of the registers, see [[MMC2]]. | |||
=== PRG ROM bank select ($A000-$AFFF) === | === PRG ROM bank select ($A000-$AFFF) === | ||
7 bit 0 | 7 bit 0 | ||
| Line 32: | Line 46: | ||
++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF | ++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF | ||
== | == Hardware == | ||
The MMC4 is implemented in a 44-pin TQFP package: [[MMC4 pinout]] | |||
Only one revision is known to exist. | Only one revision is known to exist. | ||
== | == See also == | ||
* [http://www.romhacking.net/documents/362/ NES Mapper List] by Disch | |||
* [http://nesdev.org/mmc4.txt Nintendo MMC4] (author unknown) | |||
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate. | |||
MMC4 | |||
Latest revision as of 23:09, 20 May 2020
MMC4
FxROM
FxROM
| Company | Nintendo |
| Games | 3 in NesCartDB |
| Complexity | ASIC |
| Boards | FJROM, FKROM |
| Pinout | MMC4 pinout |
| PRG ROM capacity | 256K |
| PRG ROM window | 16K + 16K fixed |
| PRG RAM capacity | 8K |
| PRG RAM window | 8K |
| CHR capacity | 128K |
| CHR window | 4K + 4K (triggered) |
| Nametable mirroring | H or V, switchable |
| Bus conflicts | No |
| IRQ | No |
| Audio | No |
| iNES mappers | 010 |
The Nintendo MMC4 is an ASIC mapper, used on the FxROM board set. The iNES format assigns mapper 10 to these boards. The chip first appeared in August 1988.
Nintendo's MMC2, used in PxROM boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left (low) pattern table. This page only explains the differences, see MMC2 for full details on the rest of the mapper.
Banks
- CPU $6000-$7FFF: 8 KB fixed PRG RAM bank
- CPU $8000-$BFFF: 16 KB switchable PRG ROM bank
- CPU $C000-$FFFF: 16 KB PRG ROM bank, fixed to the last bank
- PPU $0000-$0FFF: Two 4 KB switchable CHR ROM banks
- PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks
When the PPU reads from specific tiles in the pattern table during rendering, the MMC4 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolising the CPU.
- PPU reads $0FD8 through $0FDF: latch 0 is set to $FD
- PPU reads $0FE8 through $0FEF: latch 0 is set to $FE
- PPU reads $1FD8 through $1FDF: latch 1 is set to $FD
- PPU reads $1FE8 through $1FEF: latch 1 is set to $FE
Registers
The MMC4 has 6 registers at $A000-$AFFF, $B000-$BFFF, $C000-$CFFF, $D000-$DFFF, $E000-$EFFF and $F000-$FFFF. Only $A000-$AFFF is covered here. For the rest of the registers, see MMC2.
PRG ROM bank select ($A000-$AFFF)
7 bit 0
---- ----
xxxx PPPP
||||
++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
Hardware
The MMC4 is implemented in a 44-pin TQFP package: MMC4 pinout
Only one revision is known to exist.
See also
- NES Mapper List by Disch
- Nintendo MMC4 (author unknown)
- Comprehensive NES Mapper Document by \Firebug\, information about mapper's initial state is inaccurate.
