INES Mapper 255: Difference between revisions
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{{DEFAULTSORT:255}}[[Category:Multicart mappers]][[Category:Discrete logic mappers]] | {{DEFAULTSORT:255}}[[Category:Multicart mappers]][[Category:Discrete logic mappers]] | ||
[[iNES Mapper 255]] is apparently assigned to the ''110-in-1'' multicart. | [[iNES Mapper 255]] is apparently assigned to the ''110-in-1'' multicart. | ||
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The two latches' reset inputs are tied to 5V, so the banking register boots with random contents. | The two latches' reset inputs are tied to 5V, so the banking register boots with random contents. | ||
This looks like a duplicate of [[iNES Mapper 225]]. It's not clear why Nestopia implemented it twice. | |||
See also: https://forums.nesdev.org/viewtopic.php?p=209732#p209732 | See also: https://forums.nesdev.org/viewtopic.php?p=209732#p209732 | ||
Latest revision as of 00:03, 19 February 2023
iNES Mapper 255 is apparently assigned to the 110-in-1 multicart.
A~[1BMZ PPPP PpCC CCCC]
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+-----------++-++++ - Select 8 KiB CHR at PPU $0000
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+---++++--++------- - Select 16 KiB PRG at CPU $8000 and $C000 if Z=1
+---++++--+-------- - Select 32 KiB PRG at CPU $8000 if Z=0
|+---------------- - Select PRG bank size: 0-32K 1-16K
+----------------- - Nametable mirroring: 0-PPUA10 ("vertical") 1-PPUA11 ("horizontal")
Hardware on the board includes
- four 512 KiB ROMs for PRG
- two 512 KiB ROMs for CHR
- two 74'273 8-bit latches
- 74139
- PAL16L8 emulating a 74153
- an unpopulated footprint for a 74'670
The two latches' reset inputs are tied to 5V, so the banking register boots with random contents.
This looks like a duplicate of iNES Mapper 225. It's not clear why Nestopia implemented it twice.
See also: https://forums.nesdev.org/viewtopic.php?p=209732#p209732
