INES Mapper 148: Difference between revisions
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NewRisingSun (talk | contribs) (The "lack of bus prevention circuitry" part was highly misleading, as bus prevention circuity more commonly refers to PRG-ROM /OE being connected to inverted CPU /WR, when we're actually talking about a different address range.) |
(someone bothered to trace the photos in the flickr link and found that CPU A13 and A14 are also ORed into the bits that must not be set for a mapper write) |
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Bus conflicts: | Bus conflicts: | ||
$8000: [.... PCCC] - Select 32 KiB PRG bank and 8 KiB CHR bank | $8000: [.... PCCC] - Select 32 KiB PRG bank and 8 KiB CHR bank | ||
Sachen's SA-008-A board uses a mask of $E000 but is otherwise the same. | |||
== References == | == References == | ||
Latest revision as of 16:44, 18 June 2024
iNES Mapper 148 denotes the Sachen SA-008-A and Tengen 800008 circuit boards, which switch up to 64 KiB of PRG-ROM in 32 KiB amounts and up to 64 KiB of CHR-ROM in 8 KiB amounts using a data latch. The bit assignment of the data latch is the same as INES Mapper 079's, but unlike mapper 79, the latch register is in the CPU $8000-$FFFF range instead of $4100-$5FFF, introducing bus conflicts.
Data Latch
Mask: $8000 Bus conflicts: $8000: [.... PCCC] - Select 32 KiB PRG bank and 8 KiB CHR bank
Sachen's SA-008-A board uses a mask of $E000 but is otherwise the same.
