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(→‎Load register ($8000-$FFFF): Adds note to Load register about D0 being ignored on consecutive-cycle writes.)
 
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|boards=SKROM, SLROM,<br/>SNROM, others
|boards=SKROM, SLROM,<br/>SNROM, others
|pinout=MMC1 pinout
|pinout=MMC1 pinout
|prgmax=256K (512K)
|prgmax=256 KiB (512 KiB)
|prgpage=16K + 16K fixed or 32K
|prgpage=16 KiB + 16 KiB fixed or 32 KiB
|wrammax=32K
|wrammax=32 KiB
|wrampage=8K
|wrampage=8 KiB
|chrmax=128K
|chrmax=128 KiB
|chrpage=4K + 4K or 8K
|chrpage=4 KiB + 4 KiB or 8 KiB
|mirroring=H, V, or 1, switchable
|mirroring=H, V, or 1, switchable
|busconflicts=No
|busconflicts=No
}}
}}
[[Category:Nintendo licensed mappers]][[Category:NES 2.0 mappers with submappers]]
[[Category:Nintendo licensed mappers]][[Category:NES 2.0 mappers with submappers]]
The '''Nintendo MMC1''' is a [[MMC|mapper]] [[:Category:ASIC mappers|ASIC]] used in Nintendo's [[SxROM]] and [[NES-EVENT]] Game Pak boards. Most common SxROM boards are assigned to '''iNES Mapper 1'''. This chip first appeared in the April of 1987.
The '''Nintendo MMC1''' is a [[MMC|mapper]] [[:Category:ASIC mappers|ASIC]] used in Nintendo's [[SxROM]], [[NES-EVENT]] and '''2ME''' circuit boards. It first appeared in the April of 1987.
 
'''iNES Mapper 1''' and '''155''' denote the '''SxROM''' and '''2ME''' circuit boards mounting the MMC1B (iNES Mapper 1) or MMC1A (iNES Mapper 155) [[#ASIC Revisions|revision]] of the ASIC; Mapper 1 is used if the revision is not known or irrelevant. Two submappers of mapper 1/155 are valid:
* '''Submapper 5''' denotes the [[#SEROM, SHROM and SH1ROM|SEROM/SHROM/SH1ROM]] circuit boards with 32 KiB of unbanked PRG-ROM.
* '''Submapper 6''' denotes the Famicom Network System's '''2ME''' circuit board.
All other [[#SxROM board types|SxROM variants]] are denoted by their functional PRG/CHR-ROM/RAM sizes in the [[NES 2.0]] header. Without NES 2.0, the PRG-RAM size has to be assumed; 32 KiB are sufficient for compatibility with all known titles.
 
[[INES Mapper 105]] denotes the NES-EVENT circuit board.


== Banks ==
== Banks ==
* CPU $6000-$7FFF: 8 KB PRG RAM bank, (optional)
* CPU $6000-$7FFF: 8 KB PRG-RAM bank, (optional)
* CPU $8000-$BFFF: 16 KB PRG ROM bank, either switchable or fixed to the first bank
* CPU $8000-$BFFF: 16 KB PRG-ROM bank, either switchable or fixed to the first bank
* CPU $C000-$FFFF: 16 KB PRG ROM bank, either fixed to the last bank or switchable
* CPU $C000-$FFFF: 16 KB PRG-ROM bank, either fixed to the last bank or switchable
* PPU $0000-$0FFF: 4 KB switchable CHR bank
* PPU $0000-$0FFF: 4 KB switchable CHR bank
* PPU $1000-$1FFF: 4 KB switchable CHR bank
* PPU $1000-$1FFF: 4 KB switchable CHR bank


Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG ROM banks or to set up 32 KB PRG bankswitching (like [[BNROM]]), but most games use the default setup, which is similar to that of [[UxROM]].
Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG-ROM banks or to set up 32 KB PRG bankswitching (like [[BNROM]]), but most games use the default setup, which is similar to that of [[UxROM]].
 
== Registers ==


Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce pin count. CPU $8000-$FFFF is connected to a common shift register.
== Interface ==
Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce its pin count. CPU $8000-$FFFF is connected to a common shift register.
Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state.
Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state.
To change a register's value, the CPU writes five times with bit 7 clear and a bit of the desired value in bit 0.
To change a register's value, the CPU writes five times with bit 7 clear and one bit of the desired value in bit 0 (starting with the low bit of the value).
On the first four writes, the MMC1 shifts bit 0 into a shift register.
On the first four writes, the MMC1 shifts bit 0 into a shift register.
On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register.
On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register.
Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper registers are incompletely decoded like the [[PPU registers]]. After the fifth write, the shift register is cleared automatically, so a write to the shift register with bit 7 on to reset it is not needed.
Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper doesn't see the lower address bits (similar to the mirroring seen with [[PPU registers]]). After the fifth write, the shift register is cleared automatically, so writing again with bit 7 set to clear the shift register is not needed.
 
When the serial port is written to on consecutive cycles, it ignores every write after the first. In practice, this only happens when the CPU executes read-modify-write instructions, which first write the original value before writing the modified one on the next cycle.<ref>[http://nesdev.org/6502_cpu.txt 6502_cpu.txt]. See the section labelled Instruction Timing, subsections Absolute addressing, Read-Modify-Write instructions</ref> This restriction only applies to the data being written on bit 0; the bit 7 reset is never ignored. ''Bill & Ted's Excellent Adventure'' does a reset by using INC on a ROM location containing $FF and requires that the $00 write on the next cycle is ignored. ''Shinsenden'', however, uses illegal instruction $7F (RRA abs,X) to set bit 7 on the second write and will crash after selecting the みる (look) option if this reset is ignored.<ref>[https://forums.nesdev.org/viewtopic.php?t=23730 Forum thread:] ''Shinsenden'' crash and MMC1 reset findings</ref> This write-ignore behavior appears to be intentional and is believed to ignore all consecutive write cycles after the first even if that first write does not target the serial port.<ref>[https://forums.nesdev.org/viewtopic.php?p=91562#p91562 Forum post:] MMC1 write investigation</ref>
 


=== Examples ===
==== Shift register ====
To switch a bank, a program will execute code similar to the following:
To switch a bank, a program will execute code similar to the following:


<pre>
<pre>
;
;
; Sets the switchable PRG ROM bank to the value of A.
; Sets the switchable PRG-ROM bank to the value of A.
;
;
               ;  A          MMC1_SR  MMC1_PB
               ;  A          MMC1_SR  MMC1_PB
Line 63: Line 68:
</pre>
</pre>


But because only the fifth write sets the destination register, the following equivalent (if [[Watermarking#Instruction encoding|obfuscated]]) subroutine changes the PRG ROM bank in the same manner:
But because only the fifth write sets the destination register, the following equivalent (if [[Watermarking#Instruction encoding|obfuscated]]) subroutine changes the PRG-ROM bank in the same manner:


<pre>
<pre>
Line 79: Line 84:
</pre>
</pre>


==== Reset ====
To reset the mapper, which clears the shift register and sets the PRG-ROM bank mode to 3 (fixing the last bank at $C000 and allowing the 16 KB bank at $8000 to be switched), one need only do a single write to any ROM address with a 1 in bit 7:
<pre>
resetMapper:
  lda #$80
  sta $8000
  rts
</pre>
Commonly, reset is done with an increment on a negative value to save 2 bytes. Because increment performs two writes, first writing the old value before the incremented one, it is recommended (such as for wider emulator compatibility) that the increment target a value that is negative on both writes, such as the INC opcode ($EE) itself:
<pre>
resetMapper:
  inc resetMapper
  rts
</pre>
Note that some games do a reset write to each of the 4 registers, even though it is only necessary to do 1 reset write to any register. It is suspected these games do this because of discrete logic implementations of MMC1 on development boards such as the MMC MULTI CHECKER-02, which uses separate shift registers for each MMC1 register.<ref>[https://forums.nesdev.org/viewtopic.php?t=25065 Forum thread:] MMC MULTI CHECKER-02 development board</ref>
=== Consecutive-cycle writes ===
When the serial port is written to on consecutive cycles, it ignores every write after the first. In practice, this only happens when the CPU executes read-modify-write instructions, which first write the original value before writing the modified one on the next cycle.<ref>[http://nesdev.org/6502_cpu.txt 6502_cpu.txt]. See the section labelled Instruction Timing, subsections Absolute addressing, Read-Modify-Write instructions</ref> This restriction only applies to the data being written on bit 0; the bit 7 reset is never ignored. ''Bill & Ted's Excellent Adventure'' does a reset by using INC on a ROM location containing $FF and requires that the $00 write on the next cycle is ignored. ''Shinsenden'', however, uses illegal instruction $7F (RRA abs,X) to set bit 7 on the second write and will crash after selecting the みる (look) option if this reset is ignored.<ref>[https://forums.nesdev.org/viewtopic.php?t=23730 Forum thread:] ''Shinsenden'' crash and MMC1 reset findings</ref> This write-ignore behavior appears to be intentional and is believed to ignore all consecutive write cycles after the first even if that first write does not target the serial port.<ref>[https://forums.nesdev.org/viewtopic.php?p=91562#p91562 Forum post:] MMC1 write investigation</ref>
== Registers ==
The following description generally applies to all boards mounting an MMC1 ASIC; refer to the [[#SxROM connection variants|connection variants]] section on how some registers bits have different meanings on particular circuit boards.
=== Load register ($8000-$FFFF) ===
=== Load register ($8000-$FFFF) ===
  7  bit  0
  7  bit  0
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  +--------- A write with bit set will reset shift register
  +--------- A write with bit set will reset shift register
             and write Control with (Control OR $0C),  
             and write Control with (Control OR $0C),  
             locking PRG ROM at $C000-$FFFF to the last bank.
             locking PRG-ROM at $C000-$FFFF to the last bank.
 
On consecutive-cycle writes, writes to the shift register (D0) after the first are ignored. See [[#Consecutive-cycle_writes|Consecutive-cycle writes]] for more details.
On consecutive-cycle writes, writes to the shift register (D0) after the first are ignored.
 
=== Control (internal, $8000-$9FFF) ===
=== Control (internal, $8000-$9FFF) ===
  4bit0
  4bit0
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  CPPMM
  CPPMM
  |||||
  |||||
  |||++- [[Mirroring]] (0: one-screen, lower bank; 1: one-screen, upper bank;
  |||++- [[Nametable]] arrangement: (0: one-screen, lower bank; 1: one-screen, upper bank;
  |||              2: vertical; 3: horizontal)
  |||              2: horizontal arrangement ("vertical mirroring", PPU A10);  
  |++--- PRG ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number;
|||              3: vertical arrangement ("horizontal mirroring", PPU A11) )
  |++--- PRG-ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number;
  |                        2: fix first bank at $8000 and switch 16 KB bank at $C000;
  |                        2: fix first bank at $8000 and switch 16 KB bank at $C000;
  |                        3: fix last bank at $C000 and switch 16 KB bank at $8000)
  |                        3: fix last bank at $C000 and switch 16 KB bank at $8000)
  +----- CHR ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)
  +----- CHR-ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)


Although [//forums.nesdev.org/viewtopic.php?t=6766 some tests have found that all versions of the MMC1 seems to reliably power on in the last bank] (by setting the "PRG ROM bank mode" to 3); [//forums.nesdev.org/viewtopic.php?f=2&t=14958 other tests have found that this is fragile]. Several commercial games have reset vectors every 32 KiB, but not every 16, so evidently PRG ROM bank mode 2 doesn't seem to occur randomly on power-up.
Although [//forums.nesdev.org/viewtopic.php?t=6766 some tests have found that all versions of the MMC1 seems to reliably power on in the last bank] (by setting the "PRG-ROM bank mode" to 3); [//forums.nesdev.org/viewtopic.php?f=2&t=14958 other tests have found that this is fragile]. Several commercial games have reset vectors every 32 KiB, but not every 16, so evidently PRG-ROM bank mode 2 doesn't seem to occur randomly on power-up.


=== CHR bank 0 (internal, $A000-$BFFF) ===
=== CHR bank 0 (internal, $A000-$BFFF) ===
Line 112: Line 141:
  +++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)
  +++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)


MMC1 can do CHR banking in 4KB chunks. Known carts with CHR RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.
MMC1 can do CHR banking in 4KB chunks. Known carts with CHR-RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.


=== CHR bank 1 (internal, $C000-$DFFF) ===
=== CHR bank 1 (internal, $C000-$DFFF) ===
Line 126: Line 155:
  RPPPP
  RPPPP
  |||||
  |||||
  |++++- Select 16 KB PRG ROM bank (low bit ignored in 32 KB mode)
  |++++- Select 16 KB PRG-ROM bank (low bit ignored in 32 KB mode)
  +----- MMC1B and later: PRG RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)
  +----- MMC1B and later: PRG-RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)
         MMC1A: Bit 3 bypasses fixed bank logic in 16K mode (0: affected; 1: bypassed)
         MMC1A: Bit 3 bypasses fixed bank logic in 16K mode (0: fixed bank affects A17-A14;
 
        1: fixed bank affects A16-A14 and bit 3 directly controls A17)
The high bit does not select a PRG ROM bank. MMC1 with 512K was supported by re-using a line from the CHR banking controls. (See [[#SOROM, SUROM and SXROM|below]].)


== Hardware ==
The high bit does not select a PRG-ROM bank. MMC1 with 512 KiB was supported by re-using a line from the CHR banking controls. (See [[#SOROM, SUROM and SXROM|below]].)


At least six different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B2F, MMC1B3. Additionally, there is one unsubstantiated report about an MMC1C. The known differences relate to bit 4 of $E000.
MMC1A's 'R' bit logic was originally designed to support a hypothetical circuit board that connects the MMC1's A17 output to PRG-RAM A13, meaning a circuit board with 128 KiB of PRG-ROM and 16 KiB of PRG-RAM. Such a circuit board was never produced; games needing 16 KiB of PRG-RAM ended up using the [[#SOROM, SUROM and SXROM|SOROM]] or [[#SZROM|SZROM]] circuit boards that support more than 128 KiB of PRG-ROM and bank-switch PRG-RAM using other means.
 
* MMC1A: PRG RAM is always enabled. Two games abuse this lack of feature: they have been allocated to [[iNES Mapper 155]]. Bit 4 of $E000 causes bit 3 to directly control PRG ROM A17 instead of going through the fixed bank logic.
* MMC1B: PRG RAM is enabled by default, and $E000 bit 3 does not bypass the fixed bank.
* MMC1C: PRG RAM is (reportedly) disabled by default, and $E000 bit 3 does not bypass the fixed bank.
 
The MMC1 most commonly exists in a [[MMC1 pinout|24-pin shrink-DIP package]].  An SOIC-24 incarnation MMC1B2F has been observed inside of a JRA-PAT Famicom Network System card.
 
Boards using an MMC1 may contain a battery connected to the PRG RAM's power line to preserve the data.
Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors.
A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery as part of UL compliance. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capcity, and saves are lost much more easily on those boards.
 
Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88)
 
AX5904 is a third-party clone of the MMC1A.
 
== Variants ==
 
Because the higher CHR lines aren't used when the MMC1 mapper is used with a 8KB CHR RAM, those lines are sometimes put to other uses depending on the board:


== SxROM connection variants ==
=== SEROM, SHROM and SH1ROM ===
Boards designed for 32 KiB PRG-ROM (SEROM, SHROM, and SH1ROM), such as ''Dr. Mario'', do not connect PRG A14 to the MMC1; instead A14 is connected directly to the NES. As a result, register $E000 is completely without function, and the entire 32 KiB of PRG-ROM appear unbanked from CPU $8000-$FFFF. For compatibility with these, an emulator may switch to PRG bank 0 at power-on.
=== SNROM ===
=== SNROM ===
----
SNROM, which only supports 8 KiB of CHR-ROM/-RAM, uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG-RAM.[http://forums.nesdev.org/viewtopic.php?t=7045]
==== CHR bank 0 (internal, $A000-$BFFF) ====
==== CHR bank 0 (internal, $A000-$BFFF) ====
  4bit0
  4bit0
Line 161: Line 174:
  ExxxC
  ExxxC
  |  |
  |  |
  |  +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
  |  +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode)
  +----- PRG RAM disable (0: enable, 1: open bus)
  +----- PRG-RAM disable (0: enable, 1: open bus)


==== CHR bank 1 (internal, $C000-$DFFF) ====
==== CHR bank 1 (internal, $C000-$DFFF) ====
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  ExxxC
  ExxxC
  |  |
  |  |
  |  +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
  |  +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode)
  +----- PRG RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)
  +----- PRG-RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)
 
Both the <code>E</code> bit and the <code>R</code> bit (in standard MMC1 registers) should be clear in order for the PRG RAM to be writable or readable. This bit is more "reliable" on authentic hardware as it is implemented even in older boards with older MMC1's, while the <code>R</code> bit was only introduced later.
But because the <code>E</code> bit wasn't confirmed by the homebrew community until October 2010<ref>[http://forums.nesdev.org/viewtopic.php?t=7045 Forum topic:] NES SNROM to 512K cart?</ref>, emulators tend not to implement it.
 
=== SOROM, SUROM and SXROM ===
=== SOROM, SUROM and SXROM ===
----
All three address only 8 KiB of CHR-ROM/-RAM and use the upper CHR lines to increase the PRG-RAM size from 8 to 16 KiB (SOROM) or 32 KiB (SXROM), and to increase the PRG-ROM size from 256 to 512 KiB (SUROM and SXROM).
==== CHR bank 0 (internal, $A000-$BFFF) ====
==== CHR bank 0 (internal, $A000-$BFFF) ====
  4bit0
  4bit0
Line 182: Line 191:
  PSSxC
  PSSxC
  ||| |
  ||| |
  ||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
  ||| +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode)
  |++--- Select 8 KB PRG RAM bank
  |++--- Select 8 KB PRG-RAM bank
  +----- Select 256 KB PRG ROM bank
  +----- Select 256 KB PRG-ROM bank


==== CHR bank 1 (internal, $C000-$DFFF) ====
==== CHR bank 1 (internal, $C000-$DFFF) ====
Line 191: Line 200:
  PSSxC
  PSSxC
  ||| |
  ||| |
  ||| +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
  ||| +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode)
  |++--- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
  |++--- Select 8 KB PRG-RAM bank (ignored in 8 KB mode)
  +----- Select 256 KB PRG ROM bank (ignored in 8 KB mode)
  +----- Select 256 KB PRG-ROM bank (ignored in 8 KB mode)


The SOROM board only implements the upper <code>S</code> bit, while the SUROM board only implements the <code>P</code> bit. For SXROM, the upper <code>S</code> (bit 3) selects the SRAM's A14, and the lower <code>S</code> (bit 2) selects A13<ref>[http://forums.nesdev.org/viewtopic.php?t=4596 Forum post:] Tracing the SXROM PCB</ref>.
The SOROM board only implements the upper <code>S</code> bit, while the SUROM board only implements the <code>P</code> bit. For SXROM, the upper <code>S</code> (bit 3) selects the SRAM's A14, and the lower <code>S</code> (bit 2) selects A13<ref>[http://forums.nesdev.org/viewtopic.php?t=4596 Forum post:] Tracing the SXROM PCB</ref>.


The 256 KB PRG bank selection applies to all the PRG area, ''including the supposedly "fixed" bank''.
The 256 KB PRG bank selection applies to all the PRG area, ''including the normally "fixed" bank''. It is therefore sometimes described as an "outer bank".


In 4KB CHR bank mode, SNROM's <code>E</code> bit and SO/U/XROM's <code>P</code> and <code>S</code> bits in both CHR bank registers must be set to the same values, or the PRG ROM and/or RAM will be bankswitched/enabled as the PPU renders, in a similar fashion as [[MMC3#Hardware|MMC3]]'s scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]].
In 4KB CHR bank mode, SNROM's <code>E</code> bit and SO/U/XROM's <code>P</code> and <code>S</code> bits in both CHR bank registers must be set to the same values, or the PRG-ROM and/or RAM will be bankswitched/enabled as the PPU renders. As there is not much of a reason to use 4 KB bankswitching with CHR-RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]].


=== SZROM ===
=== SZROM ===
----
SZROM addresses only 64 KiB of CHR-ROM/-RAM and uses the remaining CHR line to increase the PRG-RAM size from 8 to 16 KiB.
==== CHR bank 0 (internal, $A000-$BFFF) ====
==== CHR bank 0 (internal, $A000-$BFFF) ====
  4bit0
  4bit0
Line 208: Line 217:
  RCCCC
  RCCCC
  |||||
  |||||
  |++++- Select 4 KB CHR ROM bank at PPU $0000 (low bit ignored in 8 KB mode)
  |++++- Select 4 KB CHR-ROM bank at PPU $0000 (low bit ignored in 8 KB mode)
  +----- Select 8 KB PRG RAM bank
  +----- Select 8 KB PRG-RAM bank


==== CHR bank 1 (internal, $C000-$DFFF) ====
==== CHR bank 1 (internal, $C000-$DFFF) ====
Line 216: Line 225:
  RCCCC
  RCCCC
  |||||
  |||||
  |++++- Select 4 KB CHR ROM bank at PPU $1000 (ignored in 8 KB mode)
  |++++- Select 4 KB CHR-ROM bank at PPU $1000 (ignored in 8 KB mode)
  +----- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
  +----- Select 8 KB PRG-RAM bank (ignored in 8 KB mode)


SZROM behaves similarly to SOROM, except that the PRG RAM bank is a controlled by a different bit, and enough CHR is present that 4K bankswitching is desirable. The only currently-known game on SZROM is ''A Ressha de Ikou''.
SZROM behaves similarly to SOROM, except that the PRG-RAM bank is a controlled by a different bit, and enough CHR is present that 4K bankswitching is desirable. The only currently-known game on SZROM is ''A Ressha de Ikou''.


SZROM can be detected by a NES2.0 header specifying 8K of PRG RAM, 8K of PRG NV RAM, and 16K or more of CHR.
SZROM can be detected by a NES2.0 header specifying 8 KiB of PRG-RAM, 8 KiB of PRG-NVRAM, and 16 KiB or more of CHR.


=== 2ME ===
=== Summary ===
----
The connection variants of SxROM that apply to registers $A000 and $C000 can be amalgamated as follows:
4bit0
-----
EDCBA
|||||
||||+- CHR A12
|||+-- CHR A13 if CHR >= 16 KiB
||+--- CHR A14 if CHR >= 32 KiB; and PRG-RAM A13 if PRG-RAM size is 32 KiB
|+---- CHR A15 if CHR >= 64 KiB; and PRG-RAM A13 if PRG-RAM size is 16 KiB
|                                or PRG-RAM A14 if PRG-RAM size is 32 KiB
+----- CHR A16 if CHR = 128 KiB; and PRG-ROM A18 if PRG-ROM size is 512 KiB
 
The <code>E</code> bit also acts as a PRG-RAM disable for SNROM (PRG-ROM size <= 256 KiB, CHR-RAM size = 8 KiB, PRG-RAM size = 8 KiB), though this is merely for write protection and not strictly required for compatible emulation.
 
The <code>D</code> bit used by SOROM (16k PRG-RAM) and SXROM (32 KiB PRG-RAM) controls a different address line depending on the board type. Using A13 for <code>D</code> with both boards and A14 for <code>C</code> will work, but will break SXROM battery save file compatibility with standard implementations.
 
== 2ME ==
This board, used with the [[Famicom Network System]] (FCNS), features 64 big-endian 16-bit words of EEPROM in addition to up to 32 KB of battery-backed PRG-RAM. Because FCNS cartridges are not on the PPU bus, all PPU-related MMC1 outputs are repurposed for EEPROM and PRG-RAM storage. The EEPROM's data output is mapped to $6000-7FFF bit 0 when enabled, and its command and data interface can be found in the 93LC46 datasheet. Note that open bus for this board is card open bus, which is open bus on the card side of the FCNS, not the console side.
This board, used with the [[Famicom Network System]] (FCNS), features 64 big-endian 16-bit words of EEPROM in addition to up to 32 KB of battery-backed PRG-RAM. Because FCNS cartridges are not on the PPU bus, all PPU-related MMC1 outputs are repurposed for EEPROM and PRG-RAM storage. The EEPROM's data output is mapped to $6000-7FFF bit 0 when enabled, and its command and data interface can be found in the 93LC46 datasheet. Note that open bus for this board is card open bus, which is open bus on the card side of the FCNS, not the console side.


Line 235: Line 260:
     | ||||
     | ||||
     | ||++- EEPROM CS (01 = enabled, otherwise disabled)
     | ||++- EEPROM CS (01 = enabled, otherwise disabled)
     | ++--- PRG ROM bank mode (see [[MMC1#Control_(internal,_$8000-$9FFF)|standard register definition]])
     | ++--- PRG-ROM bank mode (see [[MMC1#Control_(internal,_$8000-$9FFF)|standard register definition]])
     +------ EEPROM DI enable (0 = DI forced to 0, 1 = DI output enabled)
     +------ EEPROM DI enable (0 = DI forced to 0, 1 = DI output enabled)


Line 263: Line 288:
  ...D PPPP
  ...D PPPP
     | ||||
     | ||||
     | ++++- PRG ROM bank (see [[MMC1#PRG_bank_(internal,_$E000-$FFFF)|standard register definition]])
     | ++++- PRG-ROM bank (see [[MMC1#PRG_bank_(internal,_$E000-$FFFF)|standard register definition]])
     +------ $6000-7FFF disable (0 = enabled, 1 = disabled)
     +------ $6000-7FFF disable (0 = enabled, 1 = disabled)


If $6000-7FFF is disabled, then neither PRG-RAM nor EEPROM can be accessed through this region and reads return card open bus. EEPROM can still be written, however, because the DI input does not use this region.
If $6000-7FFF is disabled, then neither PRG-RAM nor EEPROM can be accessed through this region and reads return card open bus. EEPROM can still be written, however, because the DI input does not use this region.


== iNES Mapper 001 ==
== SxROM board types ==
The following SxROM boards are known to exist:
{| class="tabular"
! Board || PRG-ROM || PRG-RAM || CHR || Comments
|-
| {{nesdblink|unif_wild|SAROM|SAROM}}      || 64 KB || 8 KB || 16 / 32 / 64 KB ROM || NES only
|-
| {{nesdblink|unif_wild|SBROM|SBROM}}      || 64 KB ||  || 16 / 32 / 64 KB ROM || NES only
|-
| {{nesdblink|unif_wild|SCROM|SCROM}}      || 64 KB ||  || 128 KB ROM || NES only
|-
| {{nesdblink|unif_wild|SC1ROM|SC1ROM}}    || 64 KB || || 128 KB ROM || Uses [[7432]] for 28-pin CHR-ROM
|-
| {{nesdblink|unif_wild|SEROM|SEROM}}      || 32 KB ||  || 16 / 32 / 64 KB ROM ||
|-
| {{nesdblink|unif_wild|SFROM|SFROM}}      || 128 / 256 KB ||  || 16 / 32 / 64 KB ROM ||
|-
| {{nesdblink|unif_wild|SF1ROM|SF1ROM}}    || 256 KB || || 64 KB ROM || [http://forums.nesdev.org/viewtopic.php?p=139126#p139126 PRG uses standard 32-pin EPROM pinout]
|-
| [https://nescartdb.com/profile/view/745 SFEXPROM] || 256 KB ||  || 64 KB ROM || [http://forums.nesdev.org/viewtopic.php?t=1371 Patches PRG at runtime] to correct a bad mask ROM run.
|-
| {{nesdblink|unif_wild|SGROM|SGROM}}      || 128 / 256 KB ||  || 8 KB RAM/ROM ||
|-
| {{nesdblink|unif_wild|SHROM|SHROM}}      || 32 KB ||  || 128 KB ROM || NES only
|-
| {{nesdblink|unif_wild|SH1ROM|SH1ROM}}    || 32 KB || || 128 KB ROM || Uses [[7432]] for 28-pin CHR-ROM
|-
| {{nesdblink|unif_wild|SIROM|SIROM}}      || 32 KB || 8 KB || 16 / 32 / 64 KB ROM || Japan Only
|-
| {{nesdblink|unif_wild|SJROM|SJROM}}      || 128 / 256 KB || 8 KB || 16 / 32 / 64 KB ROM ||
|-
| {{nesdblink|unif_wild|SKROM|SKROM}}      || 128 / 256 KB || 8 KB || 128 KB ROM ||
|-
| {{nesdblink|unif_wild|SLROM|SLROM}}      || 128 / 256 KB ||  || 128 KB ROM ||
|-
| {{nesdblink|unif_wild|SL1ROM|SL1ROM}}    || 64 / 128 / 256 KB ||  || 128 KB ROM || Uses [[7432]] for 28-pin CHR-ROM
|-
| {{nesdblink|unif_wild|SL2ROM|SL2ROM}}    || 128 / 256 KB || || 128 KB ROM || [http://forums.nesdev.org/viewtopic.php?t=12657 CHR uses standard 32-pin EPROM pinout]
|-
| {{nesdblink|unif_wild|SL3ROM|SL3ROM}}    || 256 KB || || 128 KB ROM || Uses [[7432]] for 28-pin CHR-ROM
|-
| {{nesdblink|unif_wild|SLRROM|SLRROM}}    || 128 / 256 KB || || 128 KB ROM || Difference from SLROM unknown
|-
| {{nesdblink|unif_wild|SMROM|SMROM}}      || 256 KB || || 8 KB RAM || Japan Only
|-
| {{nesdblink|unif_wild|SNROM|SNROM}}      || 128 / 256 KB || 8 KB || 8 KB RAM/ROM ||
|-
| {{nesdblink|unif_wild|SOROM|SOROM}}      || 128 / 256 KB || 16 KB || 8 KB RAM/ROM ||
|-
| {{nesdblink|unif_wild|STROM|STROM}}      || colspan=4|Not MMC1, actually [[NROM]]
|-
| {{nesdblink|unif_wild|SUROM|SUROM}}      || 512 KB || 8 KB || 8 KB RAM/ROM ||
|-
| {{nesdblink|unif_wild|SXROM|SXROM}}      || 128 / 256 / 512 KB || 32 KB || 8 KB RAM/ROM || Japan Only
|-
| [https://www.crazysmart.net.au/phpBB3/viewtopic.php?f=10&t=8&p=9#p9 SZROM]  || 128 / 256 KB || 16 KB || 16-64 KB ROM || Japan Only
|}


'''iNES Mapper 001''' is used to designate the [[SxROM]] boardset, all of which use Nintendo's '''MMC1'''.
* SLxROM boards are functionally identical to SLROM, but with different chip pinouts. Some of them have an additional [[7432|74HC32]] chip to combine PPU /RD and PPU /A13 into a single enable signal for the CHR-ROM chip that has only 28 pins.
* SMROM is functionally identical to SGROM, but features two 128 KB PRG-ROM chips instead of one 256 KB. Only a very early MMC1 game in Japan, ''[https://nescartdb.com/profile/view/3777 Hokkaidou Rensa Satsujin: Ohoutsuku ni Shouyu]'', is known to have used this board, and one of very few Nintendo-made boards which combine smaller ROM chips to get a bigger ROM.
* One SNROM game for Famicom, ''[https://nescartdb.com/profile/view/3479 Morita Shogi]'', uses an 8 KiB CHR-ROM instead of CHR-RAM. The [[6264 static RAM|6264]] pinout is nearly identical to the pinout of an 8 KiB [[mask ROM pinout|mask ROM]], except for pins 26 and 27. On the 6264, these are a positive chip enable (CS2) and negative write enable (/WE) respectively; on the mask ROM, they may be additional positive chip enables. Either way, they're high during reads.


Because some MMC1 boards (e.g. SOROM, SUROM and SXROM) used the upper CHR bank select lines instead to select additional PRG ROM or PRG RAM data, these bits should be assigned as follows:
; Solder pad config (SAROM, SJROM, SKROM, SNROM, SUROM, and SXROM only):
* PRG-RAM retaining data : 'SL' disconnected, Battery, D1, D2, R1 R2 and R3 present.
* PRG-RAM not retaining data : 'SL' connected, leave slots for Battery, D1, D2, R1, R2 and R3 free.
Even if the SOROM and SZROM boards utilizes a battery, it is connected to only one PRG-RAM chip. The first RAM chip will not retain its data, but the second one will.


$A000 and $C000:
== ASIC Revisions ==
4bit0
At least six different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B2F, MMC1B3. The known differences relate to bit 4 of $E000.
-----
 
EDCBA
; MMC1A: PRG-RAM is always enabled at $6000-$7FFF. Bit 4 of $E000 causes bit 3 to directly control PRG-ROM A17 instead of going through the fixed bank logic.
|||||
; MMC1B: PRG-RAM is enabled by default but can by disabled by bit 4 of $E000. $E000 bit 3 never bypasses the fixed bank.
||||+- CHR A12
|||+-- CHR A13 if CHR >= 16k
||+--- CHR A14 if CHR >= 32k; and PRG RAM A13 if PRG RAM = 32k
|+---- CHR A15 if CHR >= 64k; and PRG RAM A13 if PRG RAM = 16k
|                              or PRG RAM A14 if PRG RAM = 32k
+----- CHR A16 if CHR = 128k; and PRG ROM A18 if PRG ROM = 512k


The <code>E</code> bit also acts as a PRG RAM disable for SNROM (PRG ROM <= 256k, CHR RAM = 8k, PRG RAM = 8k), though this is merely for write protection and not strictly required for compatible emulation.
The MMC1 most commonly exists in a [[MMC1 pinout|24-pin shrink-DIP package]].  An SOIC-24 incarnation MMC1B2F has been observed inside of a JRA-PAT Famicom Network System card.


The <code>D</code> bit used by SOROM (16k PRG RAM) and SXROM (32k PRG RAM) controls a different address line depending on the board type. Using A13 for <code>D</code> with both boards and A14 for <code>C</code> will work, but will break SXROM save file compatibility with correct implementations.
Boards using an MMC1 may contain a battery connected to the PRG-RAM's power line to preserve the data. Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors. A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery as part of UL compliance. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capacity, and saves are lost much more easily on those boards.


[[NES 2.0]] is required to specify PRG-RAM size. Without NES 2.0 the PRG-RAM size has to be assumed (32k may be sufficient for compatibility).
Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88). Two games ([https://nescartdb.com/profile/view/3736 1], [https://nescartdb.com/profile/view/3458 2]) are known to rely on MMC1A behavior, writing values between $10 and $1F to the PRG bank register, write to WRAM at $6000-$7FFF, and expect the write to succeed.


Boards designed for 32k PRG-ROM (SEROM, SHROM, and SH1ROM) do not connect PRG A14 to the MMC1, disabling PRG banking. For compatibility with these, the emulator may switch to PRG bank 0 at power-on. SIROM supports banked 32k PRG, however.
AX5904 is a third-party clone of the MMC1A.


== References ==
== References ==
Line 302: Line 382:
*[http://nesdev.org/mmc1.txt "Nintendo MMC1 info for 8-bit NES carts" by Matthew J. Richey]
*[http://nesdev.org/mmc1.txt "Nintendo MMC1 info for 8-bit NES carts" by Matthew J. Richey]
*[http://kevtris.org/mappers/mmc1/index.html MMC1 doc by Kevin Horton]
*[http://kevtris.org/mappers/mmc1/index.html MMC1 doc by Kevin Horton]
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information on SUROM/SXROM carts (512k carts, 1024k carts) is inaccurate
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information on SUROM/SXROM carts (512 KiB carts, 1024 KiB carts) is inaccurate
* US Patent 4,949,298
*[https://patents.google.com/patent/US4949298A/en US Patent 4,949,298]
*[https://forums.nesdev.org/viewtopic.php?t=23619 Forum topic "MMC1A fixed bank behavior difference" with test ROM, January 2022]


[[Category:Mappers with large PRG RAM]][[Category:Mappers with single-screen mirroring]]
[[Category:Mappers with large PRG RAM]][[Category:Mappers with single-screen mirroring]]

Latest revision as of 00:23, 9 November 2024

MMC1
SxROM
Company Nintendo, others
Games 390 in NesCartDB
Complexity ASIC
Boards SKROM, SLROM,
SNROM, others
Pinout MMC1 pinout
PRG ROM capacity 256 KiB (512 KiB)
PRG ROM window 16 KiB + 16 KiB fixed or 32 KiB
PRG RAM capacity 32 KiB
PRG RAM window 8 KiB
CHR capacity 128 KiB
CHR window 4 KiB + 4 KiB or 8 KiB
Nametable mirroring H, V, or 1, switchable
Bus conflicts No
IRQ No
Audio No
iNES mappers 001, 105, 155

The Nintendo MMC1 is a mapper ASIC used in Nintendo's SxROM, NES-EVENT and 2ME circuit boards. It first appeared in the April of 1987.

iNES Mapper 1 and 155 denote the SxROM and 2ME circuit boards mounting the MMC1B (iNES Mapper 1) or MMC1A (iNES Mapper 155) revision of the ASIC; Mapper 1 is used if the revision is not known or irrelevant. Two submappers of mapper 1/155 are valid:

  • Submapper 5 denotes the SEROM/SHROM/SH1ROM circuit boards with 32 KiB of unbanked PRG-ROM.
  • Submapper 6 denotes the Famicom Network System's 2ME circuit board.

All other SxROM variants are denoted by their functional PRG/CHR-ROM/RAM sizes in the NES 2.0 header. Without NES 2.0, the PRG-RAM size has to be assumed; 32 KiB are sufficient for compatibility with all known titles.

INES Mapper 105 denotes the NES-EVENT circuit board.

Banks

  • CPU $6000-$7FFF: 8 KB PRG-RAM bank, (optional)
  • CPU $8000-$BFFF: 16 KB PRG-ROM bank, either switchable or fixed to the first bank
  • CPU $C000-$FFFF: 16 KB PRG-ROM bank, either fixed to the last bank or switchable
  • PPU $0000-$0FFF: 4 KB switchable CHR bank
  • PPU $1000-$1FFF: 4 KB switchable CHR bank

Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG-ROM banks or to set up 32 KB PRG bankswitching (like BNROM), but most games use the default setup, which is similar to that of UxROM.

Interface

Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce its pin count. CPU $8000-$FFFF is connected to a common shift register. Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state. To change a register's value, the CPU writes five times with bit 7 clear and one bit of the desired value in bit 0 (starting with the low bit of the value). On the first four writes, the MMC1 shifts bit 0 into a shift register. On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register. Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper doesn't see the lower address bits (similar to the mirroring seen with PPU registers). After the fifth write, the shift register is cleared automatically, so writing again with bit 7 set to clear the shift register is not needed.

Examples

Shift register

To switch a bank, a program will execute code similar to the following: 

;
; Sets the switchable PRG-ROM bank to the value of A.
;
              ;  A          MMC1_SR  MMC1_PB
setPRGBank:   ;  000edcba    10000             Start with an empty shift register (SR).  The 1 is used
  sta $E000   ;  000edcba -> a1000             to detect when the SR has become full.
  lsr a       ; >0000edcb    a1000
  sta $E000   ;  0000edcb -> ba100
  lsr a       ; >00000edc    ba100
  sta $E000   ;  00000edc -> cba10
  lsr a       ; >000000ed    cba10
  sta $E000   ;  000000ed -> dcba1             Once a 1 is shifted into the last position, the SR is full.
  lsr a       ; >0000000e    dcba1             
  sta $E000   ;  0000000e    dcba1 -> edcba    A write with the SR full copies D0 and the SR to a bank register
              ;              10000             ($E000-$FFFF means PRG bank number) and then clears the SR.
  rts

But because only the fifth write sets the destination register, the following equivalent (if obfuscated) subroutine changes the PRG-ROM bank in the same manner: 

setPRGBank:
  sta $8765
  lsr a
  sta $FACE
  lsr a
  sta $BA11
  lsr a
  sta $AD2E
  lsr a
  sta $EAD5
  rts

Reset

To reset the mapper, which clears the shift register and sets the PRG-ROM bank mode to 3 (fixing the last bank at $C000 and allowing the 16 KB bank at $8000 to be switched), one need only do a single write to any ROM address with a 1 in bit 7: 

resetMapper:
  lda #$80
  sta $8000
  rts

Commonly, reset is done with an increment on a negative value to save 2 bytes. Because increment performs two writes, first writing the old value before the incremented one, it is recommended (such as for wider emulator compatibility) that the increment target a value that is negative on both writes, such as the INC opcode ($EE) itself: 

resetMapper:
  inc resetMapper
  rts

Note that some games do a reset write to each of the 4 registers, even though it is only necessary to do 1 reset write to any register. It is suspected these games do this because of discrete logic implementations of MMC1 on development boards such as the MMC MULTI CHECKER-02, which uses separate shift registers for each MMC1 register.[1]

Consecutive-cycle writes

When the serial port is written to on consecutive cycles, it ignores every write after the first. In practice, this only happens when the CPU executes read-modify-write instructions, which first write the original value before writing the modified one on the next cycle.[2] This restriction only applies to the data being written on bit 0; the bit 7 reset is never ignored. Bill & Ted's Excellent Adventure does a reset by using INC on a ROM location containing $FF and requires that the $00 write on the next cycle is ignored. Shinsenden, however, uses illegal instruction $7F (RRA abs,X) to set bit 7 on the second write and will crash after selecting the みる (look) option if this reset is ignored.[3] This write-ignore behavior appears to be intentional and is believed to ignore all consecutive write cycles after the first even if that first write does not target the serial port.[4]

Registers

The following description generally applies to all boards mounting an MMC1 ASIC; refer to the connection variants section on how some registers bits have different meanings on particular circuit boards.

Load register ($8000-$FFFF)

7  bit  0
---- ----
Rxxx xxxD
|       |
|       +- Data bit to be shifted into shift register, LSB first
+--------- A write with bit set will reset shift register
            and write Control with (Control OR $0C), 
            locking PRG-ROM at $C000-$FFFF to the last bank.

On consecutive-cycle writes, writes to the shift register (D0) after the first are ignored. See Consecutive-cycle writes for more details.

Control (internal, $8000-$9FFF)

4bit0
-----
CPPMM
|||||
|||++- Nametable arrangement: (0: one-screen, lower bank; 1: one-screen, upper bank;
|||               2: horizontal arrangement ("vertical mirroring", PPU A10); 
|||               3: vertical arrangement ("horizontal mirroring", PPU A11) )
|++--- PRG-ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number;
|                         2: fix first bank at $8000 and switch 16 KB bank at $C000;
|                         3: fix last bank at $C000 and switch 16 KB bank at $8000)
+----- CHR-ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)

Although some tests have found that all versions of the MMC1 seems to reliably power on in the last bank (by setting the "PRG-ROM bank mode" to 3); other tests have found that this is fragile. Several commercial games have reset vectors every 32 KiB, but not every 16, so evidently PRG-ROM bank mode 2 doesn't seem to occur randomly on power-up.

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
CCCCC
|||||
+++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)

MMC1 can do CHR banking in 4KB chunks. Known carts with CHR-RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
CCCCC
|||||
+++++- Select 4 KB CHR bank at PPU $1000 (ignored in 8 KB mode)

PRG bank (internal, $E000-$FFFF)

4bit0
-----
RPPPP
|||||
|++++- Select 16 KB PRG-ROM bank (low bit ignored in 32 KB mode)
+----- MMC1B and later: PRG-RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)
       MMC1A: Bit 3 bypasses fixed bank logic in 16K mode (0: fixed bank affects A17-A14;
       1: fixed bank affects A16-A14 and bit 3 directly controls A17)

The high bit does not select a PRG-ROM bank. MMC1 with 512 KiB was supported by re-using a line from the CHR banking controls. (See below.)

MMC1A's 'R' bit logic was originally designed to support a hypothetical circuit board that connects the MMC1's A17 output to PRG-RAM A13, meaning a circuit board with 128 KiB of PRG-ROM and 16 KiB of PRG-RAM. Such a circuit board was never produced; games needing 16 KiB of PRG-RAM ended up using the SOROM or SZROM circuit boards that support more than 128 KiB of PRG-ROM and bank-switch PRG-RAM using other means.

SxROM connection variants

SEROM, SHROM and SH1ROM

Boards designed for 32 KiB PRG-ROM (SEROM, SHROM, and SH1ROM), such as Dr. Mario, do not connect PRG A14 to the MMC1; instead A14 is connected directly to the NES. As a result, register $E000 is completely without function, and the entire 32 KiB of PRG-ROM appear unbanked from CPU $8000-$FFFF. For compatibility with these, an emulator may switch to PRG bank 0 at power-on.

SNROM

SNROM, which only supports 8 KiB of CHR-ROM/-RAM, uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG-RAM.[1]

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
ExxxC
|   |
|   +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode)
+----- PRG-RAM disable (0: enable, 1: open bus)

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
ExxxC
|   |
|   +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode)
+----- PRG-RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)

SOROM, SUROM and SXROM

All three address only 8 KiB of CHR-ROM/-RAM and use the upper CHR lines to increase the PRG-RAM size from 8 to 16 KiB (SOROM) or 32 KiB (SXROM), and to increase the PRG-ROM size from 256 to 512 KiB (SUROM and SXROM).

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG-RAM bank
+----- Select 256 KB PRG-ROM bank

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG-RAM bank (ignored in 8 KB mode)
+----- Select 256 KB PRG-ROM bank (ignored in 8 KB mode)

The SOROM board only implements the upper S bit, while the SUROM board only implements the P bit. For SXROM, the upper S (bit 3) selects the SRAM's A14, and the lower S (bit 2) selects A13[5].

The 256 KB PRG bank selection applies to all the PRG area, including the normally "fixed" bank. It is therefore sometimes described as an "outer bank".

In 4KB CHR bank mode, SNROM's E bit and SO/U/XROM's P and S bits in both CHR bank registers must be set to the same values, or the PRG-ROM and/or RAM will be bankswitched/enabled as the PPU renders. As there is not much of a reason to use 4 KB bankswitching with CHR-RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.

SZROM

SZROM addresses only 64 KiB of CHR-ROM/-RAM and uses the remaining CHR line to increase the PRG-RAM size from 8 to 16 KiB.

CHR bank 0 (internal, $A000-$BFFF)

4bit0
-----
RCCCC
|||||
|++++- Select 4 KB CHR-ROM bank at PPU $0000 (low bit ignored in 8 KB mode)
+----- Select 8 KB PRG-RAM bank

CHR bank 1 (internal, $C000-$DFFF)

4bit0
-----
RCCCC
|||||
|++++- Select 4 KB CHR-ROM bank at PPU $1000 (ignored in 8 KB mode)
+----- Select 8 KB PRG-RAM bank (ignored in 8 KB mode)

SZROM behaves similarly to SOROM, except that the PRG-RAM bank is a controlled by a different bit, and enough CHR is present that 4K bankswitching is desirable. The only currently-known game on SZROM is A Ressha de Ikou.

SZROM can be detected by a NES2.0 header specifying 8 KiB of PRG-RAM, 8 KiB of PRG-NVRAM, and 16 KiB or more of CHR.

Summary

The connection variants of SxROM that apply to registers $A000 and $C000 can be amalgamated as follows: 

4bit0
-----
EDCBA
|||||
||||+- CHR A12
|||+-- CHR A13 if CHR >= 16 KiB
||+--- CHR A14 if CHR >= 32 KiB; and PRG-RAM A13 if PRG-RAM size is 32 KiB
|+---- CHR A15 if CHR >= 64 KiB; and PRG-RAM A13 if PRG-RAM size is 16 KiB
|                                or PRG-RAM A14 if PRG-RAM size is 32 KiB
+----- CHR A16 if CHR = 128 KiB; and PRG-ROM A18 if PRG-ROM size is 512 KiB

The E bit also acts as a PRG-RAM disable for SNROM (PRG-ROM size <= 256 KiB, CHR-RAM size = 8 KiB, PRG-RAM size = 8 KiB), though this is merely for write protection and not strictly required for compatible emulation.

The D bit used by SOROM (16k PRG-RAM) and SXROM (32 KiB PRG-RAM) controls a different address line depending on the board type. Using A13 for D with both boards and A14 for C will work, but will break SXROM battery save file compatibility with standard implementations.

2ME

This board, used with the Famicom Network System (FCNS), features 64 big-endian 16-bit words of EEPROM in addition to up to 32 KB of battery-backed PRG-RAM. Because FCNS cartridges are not on the PPU bus, all PPU-related MMC1 outputs are repurposed for EEPROM and PRG-RAM storage. The EEPROM's data output is mapped to $6000-7FFF bit 0 when enabled, and its command and data interface can be found in the 93LC46 datasheet. Note that open bus for this board is card open bus, which is open bus on the card side of the FCNS, not the console side.

2ME is assigned NES 2.0 MMC1 submapper 6 and uses an MMC1B.

Control (internal, $8000-9FFF)

7  bit  0
---- ----
...I PPEE
   | ||||
   | ||++- EEPROM CS (01 = enabled, otherwise disabled)
   | ++--- PRG-ROM bank mode (see standard register definition)
   +------ EEPROM DI enable (0 = DI forced to 0, 1 = DI output enabled)

The graphics-related bits here are repurposed for EEPROM enables. Because the MMC1's PPU A12-10 inputs are grounded on the 2ME board, settings that would normally vary based on PPU fetches such as the nametable arrangement and active CHR register are instead fixed.

  • The CIRAM A10 output is used as the EEPROM's CS input and will be always true in upper-bank single screen arrangement and always false otherwise.
  • The lowest CHR register bit is used for the EEPROM's DI input, but can only be non-zero in 4 KB banking mode. The second CHR register ($C000-DFFF) is unused in this mode because the PPU inputs are fixed such that they'll never point into the upper half of the pattern table space.

CHR bank 0 (internal, $A000-BFFF)

7  bit  0
---- ----
...O RRCI
   | ||||
   | |||+- EEPROM DI
   | ||+-- EEPROM CLK
   | |+--- PRG-RAM A13
   | +---- PRG-RAM A14
   +------ PRG-RAM /CE, and EEPROM DO +OE (0 = PRG-RAM enabled, 1 = EEPROM DO enabled)
  • EEPROM DI allows sending commands or data to the EEPROM. It is forced to 0 if 4 KB banking is not enabled via $8000 bit 4.
  • EEPROM CLK is used to transition to the next bit when reading from or writing to the EEPROM.
  • PRG-RAM banking uses the same bit order as SXROM.
  • The PRG-RAM /CE and EEPROM DO +OE bit acts as a selector for $6000-7FFF between PRG-RAM access and EEPROM read. The PRG-RAM enable matches the behavior of SNROM. While EEPROM is selected, bits 7-1 always return card open bus and bit 0 returns any data currently outputted by the EEPROM or card open bus otherwise.

PRG bank (internal, $E000-FFFF)

7  bit  0
---- ----
...D PPPP
   | ||||
   | ++++- PRG-ROM bank (see standard register definition)
   +------ $6000-7FFF disable (0 = enabled, 1 = disabled)

If $6000-7FFF is disabled, then neither PRG-RAM nor EEPROM can be accessed through this region and reads return card open bus. EEPROM can still be written, however, because the DI input does not use this region.

SxROM board types

The following SxROM boards are known to exist:

Board PRG-ROM PRG-RAM CHR Comments
SAROM 64 KB 8 KB 16 / 32 / 64 KB ROM NES only
SBROM 64 KB 16 / 32 / 64 KB ROM NES only
SCROM 64 KB 128 KB ROM NES only
SC1ROM 64 KB 128 KB ROM Uses 7432 for 28-pin CHR-ROM
SEROM 32 KB 16 / 32 / 64 KB ROM
SFROM 128 / 256 KB 16 / 32 / 64 KB ROM
SF1ROM 256 KB 64 KB ROM PRG uses standard 32-pin EPROM pinout
SFEXPROM 256 KB 64 KB ROM Patches PRG at runtime to correct a bad mask ROM run.
SGROM 128 / 256 KB 8 KB RAM/ROM
SHROM 32 KB 128 KB ROM NES only
SH1ROM 32 KB 128 KB ROM Uses 7432 for 28-pin CHR-ROM
SIROM 32 KB 8 KB 16 / 32 / 64 KB ROM Japan Only
SJROM 128 / 256 KB 8 KB 16 / 32 / 64 KB ROM
SKROM 128 / 256 KB 8 KB 128 KB ROM
SLROM 128 / 256 KB 128 KB ROM
SL1ROM 64 / 128 / 256 KB 128 KB ROM Uses 7432 for 28-pin CHR-ROM
SL2ROM 128 / 256 KB 128 KB ROM CHR uses standard 32-pin EPROM pinout
SL3ROM 256 KB 128 KB ROM Uses 7432 for 28-pin CHR-ROM
SLRROM 128 / 256 KB 128 KB ROM Difference from SLROM unknown
SMROM 256 KB 8 KB RAM Japan Only
SNROM 128 / 256 KB 8 KB 8 KB RAM/ROM
SOROM 128 / 256 KB 16 KB 8 KB RAM/ROM
STROM Not MMC1, actually NROM
SUROM 512 KB 8 KB 8 KB RAM/ROM
SXROM 128 / 256 / 512 KB 32 KB 8 KB RAM/ROM Japan Only
SZROM 128 / 256 KB 16 KB 16-64 KB ROM Japan Only
  • SLxROM boards are functionally identical to SLROM, but with different chip pinouts. Some of them have an additional 74HC32 chip to combine PPU /RD and PPU /A13 into a single enable signal for the CHR-ROM chip that has only 28 pins.
  • SMROM is functionally identical to SGROM, but features two 128 KB PRG-ROM chips instead of one 256 KB. Only a very early MMC1 game in Japan, Hokkaidou Rensa Satsujin: Ohoutsuku ni Shouyu, is known to have used this board, and one of very few Nintendo-made boards which combine smaller ROM chips to get a bigger ROM.
  • One SNROM game for Famicom, Morita Shogi, uses an 8 KiB CHR-ROM instead of CHR-RAM. The 6264 pinout is nearly identical to the pinout of an 8 KiB mask ROM, except for pins 26 and 27. On the 6264, these are a positive chip enable (CS2) and negative write enable (/WE) respectively; on the mask ROM, they may be additional positive chip enables. Either way, they're high during reads.
Solder pad config (SAROM, SJROM, SKROM, SNROM, SUROM, and SXROM only)
  • PRG-RAM retaining data : 'SL' disconnected, Battery, D1, D2, R1 R2 and R3 present.
  • PRG-RAM not retaining data : 'SL' connected, leave slots for Battery, D1, D2, R1, R2 and R3 free.

Even if the SOROM and SZROM boards utilizes a battery, it is connected to only one PRG-RAM chip. The first RAM chip will not retain its data, but the second one will.

ASIC Revisions

At least six different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B2F, MMC1B3. The known differences relate to bit 4 of $E000.

MMC1A
PRG-RAM is always enabled at $6000-$7FFF. Bit 4 of $E000 causes bit 3 to directly control PRG-ROM A17 instead of going through the fixed bank logic.
MMC1B
PRG-RAM is enabled by default but can by disabled by bit 4 of $E000. $E000 bit 3 never bypasses the fixed bank.

The MMC1 most commonly exists in a 24-pin shrink-DIP package. An SOIC-24 incarnation MMC1B2F has been observed inside of a JRA-PAT Famicom Network System card.

Boards using an MMC1 may contain a battery connected to the PRG-RAM's power line to preserve the data. Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors. A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery as part of UL compliance. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capacity, and saves are lost much more easily on those boards.

Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88). Two games (1, 2) are known to rely on MMC1A behavior, writing values between $10 and $1F to the PRG bank register, write to WRAM at $6000-$7FFF, and expect the write to succeed.

AX5904 is a third-party clone of the MMC1A.

References

  1. ↑ Forum thread: MMC MULTI CHECKER-02 development board
  2. ↑ 6502_cpu.txt. See the section labelled Instruction Timing, subsections Absolute addressing, Read-Modify-Write instructions
  3. ↑ Forum thread: Shinsenden crash and MMC1 reset findings
  4. ↑ Forum post: MMC1 write investigation
  5. ↑ Forum post: Tracing the SXROM PCB

See also

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