VRC6: Difference between revisions

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(2 KiB registers are not necessary seven bits wide.)
(A #053330 VRC6 (harvested from a Madara cartridge) has been decapped and revealed to be an SLA7340 CMOS gate array, very similar to the NEC MMC3B/MMC3C)
 
(66 intermediate revisions by 10 users not shown)
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[[Category:ASIC mappers]]
{{Infobox_iNES_mapper
The Konami's VRC6 [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]] comes in two variants.  The register descriptions given here are as they exist in ''Akumajou Densetsu'' ([[iNES Mapper 024]]).  The A0 and A1 lines are switched in ''Madara'' and ''Esper Dream 2'' ([[iNES Mapper 026]]), so for those games, adjustments will need to be made ($x001 becomes $x002 and vice versa).
|name=VRC6
|company=Konami
|mapper=24
|nescartdbgames=3
|othermappers=[[iNES Mapper 026|026]]
|complexity=ASIC
|boards=351951, 351949A
|pinout=VRC6 pinout
|prgmax=256K
|prgpage=16K + 8K
|wrammax=8K
|wrampage=8K
|chrmax=256K
|chrpage=1K
|mirroring=H, V, or 1, switchable
|busconflicts=No
|irq=Yes
|audio=[[VRC6_audio|Yes]]
}}
[[Category:ASIC mappers]][[Category:Mappers with ROM nametables]][[Category:Mappers with cycle IRQs]][[Category:Mappers with single-screen mirroring]]
The Konami's '''VRC6''' [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]] comes in two variants:
* '''VRC6a''' - '''iNES Mapper 024''' used for ''Akumajou Densetsu'' (Konami PCB 351951).
* '''VRC6b''' - '''iNES Mapper 026''' used for ''Madara'' and ''Esper Dream 2'' (Konami PCB 351949A).
 
The difference between the two variants switches the A0 and A1 lines. The registers described on this page are for mapper 24, but for mapper 26 the register addresses must be adjusted ($x001 becomes $x002 and vice versa).
 
See [[VRC6 pinout]] for chip pinout.




__TOC__
__TOC__


== Banks ==
=== CPU ===
* $6000-$7FFF: 8 KB PRG-RAM bank, fixed
* $8000-$BFFF: 16 KB switchable PRG ROM bank
* $C000-$DFFF: 8 KB switchable PRG ROM bank
* $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank


== Overview ==
=== PPU ===
* PRG ROM size: Up to 256 KB
* $0000-$03FF: 1 KB switchable CHR ROM bank
* PRG ROM bank size: 16 KB at $8000, 8 KB at $C000
* $0400-$07FF: 1 KB switchable CHR ROM bank
* PRG RAM: Up to 8 KB
* $0800-$0BFF: 1 KB switchable CHR ROM bank
* CHR capacity: Up to 256 KB ROM
* $0C00-$0FFF: 1 KB switchable CHR ROM bank
* CHR bank size: 1 KB
* $1000-$13FF: 1 KB switchable CHR ROM bank
* Nametable [[mirroring]]: Controlled by mapper
* $1400-$17FF: 1 KB switchable CHR ROM bank
* Subject to [[bus conflict]]s: No
* $1800-$1BFF: 1 KB switchable CHR ROM bank
 
* $1C00-$1FFF: 1 KB switchable CHR ROM bank
See [[VRC6 pinout]] for chip pinout.


== Registers ==
== Registers ==


Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)
Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)
The addresses described here are for mapper 24. The registers for mapper 26 can be found by swapping bits 0 and 1 of the address.
    variant  lines    registers                      Mapper Number
    =================================================================
    VRC6a:    A0, A1    $x000, $x001, $x002, $x003      024
    VRC6b:    A1, A0    $x000, $x002, $x001, $x003      026


=== 16k PRG Select ($8000-$8003) ===
=== 16k PRG Select ($8000-$8003) ===
Line 27: Line 65:
  .... PPPP
  .... PPPP
       ||||
       ||||
       ++++- Select 16 KB PRG ROM at $8000
       ++++- Select 16 KB PRG ROM bank at $8000-$BFFF


=== 8k PRG Select ($C000-$C003) ===
=== 8k PRG Select ($C000-$C003) ===
Line 35: Line 73:
  ...P PPPP
  ...P PPPP
     | ||||
     | ||||
     +-++++- Select 8 KB PRG ROM at $C000
     +-++++- Select 8 KB PRG ROM bank at $C000-$DFFF


=== PPU Banking Style ($B003) ===
=== PPU Banking Style ($B003) ===
Line 43: Line 81:
  W.PN MMDD
  W.PN MMDD
  | || ||||
  | || ||||
  | || ||++- PPU addressing mode; see below
  | || ||++- PPU banking mode; see below
  | || ++--- [[Mirroring]] varies by addressing mode, see below
  | || ++--- [[Mirroring]] varies by banking mode, see below
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
  | +------- CHR A10 is 1: subject to further rules 0: according to the latched value
  | +------- CHR A10 is 1: subject to further rules 0: according to the latched value
  +--------- PRG RAM enable
  +--------- PRG RAM enable


The VRC6 supports the use of a larger RAM to provide more nametables. However, no games used any more than the two from the Famicom's built-in CIRAM.
The VRC6 supports the use of a larger RAM to provide more nametables. However, the three commercial VRC6 games neither provided extra nametable RAM, nor used ROM nametables. As a result these games only ever write the values $20, $24, $28, $2C, $A0, $A4, $A8, and $AC to this register.


==== Nametable control in mode 0 ====
CIRAM A10 is always connected to CHR A10, and bit 5 affects the behaviour of this signal (see below for details). The commercial games always left this bit set.
If the $20s bit is set, CHR A10 is connected according to the $04s and $08s bits as follows:
 
=== CHR Select 0…7 ($Dxxx, $Exxx) ===
 
For brevity, we refer to the registers at $D000 through $D003 and $E000 through $E003 as R0 through R7.
 
The lower 3 bits of the $B003 register affect where the registers are used:
{| class="wikitable"
{| class="wikitable"
| 0 || vertical mirroring || CHR A10 = PPU A10
! [$B003] & $03 → !! style="width:2em;"|0 !! style="width:2em;"|1 !! 2 or 3
|-
|-
| 4 || horizontal mirroring || CHR A10 = PPU A11
! CHR bank !! colspan=3|Register used
|-
|-
| 8 || one-screen lower || CHR A10 = ground
| $0000-$03FF || R0 || rowspan=2|R0 || R0
|-
|-
| 12 || one-screen upper || CHR A10 = vcc
| $0400-$07FF || R1 || R1
|-
| $0800-$0BFF || R2 || rowspan=2|R1 || R2
|-
| $0C00-$0FFF || R3 || R3
|-
| $1000-$13FF || R4 || rowspan=2|R2 || rowspan=2|R4
|-
| $1400-$17FF || R5
|-
| $1800-$1BFF || R6 || rowspan=2|R3 || rowspan=2|R5
|-
| $1C00-$1FFF || R7
|}
|}


The upper address lines, regardless of whether the $20s bit is set, are filled with the values of CHR select 6 and 7. They are laid out according to the $04s bit:
{| class="wikitable"
{| class="wikitable"
| 0 || vertical ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
! [$B003] & $07 → !! 0, 6, or 7 !! style="width:4em;"|1 or 5 !! 2, 3, or 4
|-
! Nametable bank !! colspan=3|Register used
|-
|-
| 4 || horizontal ''layout'' || CHR A11…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
| $2000-$23FF || R6 || R4 || R6
|-
| $2400-$27FF || R6 || R5 || R7
|-
| $2800-$2BFF || R7 || R6 || R6
|-
| $2C00-$2FFF || R7 || R7 || R7
|}
|}


If the $20s bit is clear, CHR A10 follows the rest of the address lines.
When bit 5 of $B003 is clear, CHR/CIRAM A10 will be controlled directly by the register LSB, causing 2 KiB banks to have duplicate 1 KiB halves.
Existing Konami games did not use this configuration. This was intended for a different PCB (never used) where PPU A10 directly controls CHR A10 instead, permitting 512 KiB of CHR-ROM.


==== Nametable control in mode 1 ====
When bit 5 of $B003 is set, 2 KiB pattern table banks pass PPU A10 through (ignoring the LSB of the register). Nametables apply different rules at the same time: see below.
The values written to CHRSEL[4…7] specify the banks used for nametables, without further modification.


For the 2KiB pattern table banks,
==== Mirroring ====
if the $20s bit is set, CHR A10 = PPU A10.
If the $20s bit is clear, CHR A10 parallels all the upper bits in CHRSEL[0…3]. It is then assumed that PPU A10 is connected to CHRROM separately.


The $04s and $08s bits are ignored.
With $B003:5 set, there are four different modes corresponding to $B003 & 3 that each have 4 nametable mirroring settings. Only mode 0 was used by Konami's commercial games.


==== Nametable control in mode 2 ====
===== Mode 0 =====
The value written to CHRSEL[6] specifies the bank used in lieu of CIRAM $000-$3FF.
The value written to CHRSEL[7] specifies the bank used in lieu of CIRAM $400-$7FF.


These are then placed into the nametables according to the $04s bit, using the opposite table as mode 0:
{| class="wikitable"
{| class="wikitable"
| 0 || horizontal ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A10,CHRSEL[6],CHRSEL[7])
! [$B003] & $F !!  $0 !!  $4 !!  $8 !!  $C
|-
! Mirroring
| vertical || horizontal || 1-screen A || 1-screen B
|-
|-
| 4 || vertical ''layout'' || CHR A10…A17 = MULTIPLEX(PPU A11,CHRSEL[6],CHRSEL[7])
! CIRAM A10
| PPU A10  || PPU A11    || Ground (0) || Vcc (1)
|}
|}


These are then placed into the nametables according to the $04s bit, using the same table as mode 0.
This mode was not intended for use with ROM nametables ($B003:4 set), because it overrides the LSB of the nametable registers with the signal intended for CIRAM A10.
Because R6 and R7 are already in use to control the pattern banks, this is not very suitable if combined with ROM nametables ([[#Mode 3|Mode 3]] is designed for that instead).


The $20s bit only affects the two pattern table banks, using the same rule as given for mode 1.
{| class="wikitable"
! [$B003] & $F !!  $0 !!  $4 !!  $8 !!  $C
|-
! Mirroring
| horizontal pairs<br/> 2 KiB spread || vertical pairs<br/> 2 KiB spread || horizontal mirroring<br/> 1 KiB (even only) || vertical mirroring<br/> 1 KiB (odd only)
|-
! $2000-$23FF
| R6 even || R6 even || R6 even || R6 odd
|-
! $2400-$27FF
| R6 odd  || R7 even || R6 even || R7 odd
|-
! $2800-$2BFF
| R7 even || R6 odd  || R7 even || R6 odd
|-
! $2C00-$2FFF
| R7 odd  || R7 odd  || R7 even || R7 odd
|-
! Mode 3 equivalent
| $7 || $3 || $F || $B
|}


The only way to get one-screen mirroring is by writing the same value to both CHRSEL[6] and [7].
===== Mode 1 =====
Mode 1 uses R4-R7 to directly control 4-screen mapping. This is very effective with ROM nametables ($B003:4 set), but the LSB of each register still applies when using CIRAM.


The $08s bit is ignored.
{| class="wikitable"
 
! [$B003] & $F !!  $1 !!  $5 !!  $9 !!  $D
This behavior is identical to the [[iNES Mapper 068|Sunsoft 4]] mapper.
|-
 
! Mirroring
==== Nametable control in mode 3 ====
| colspan=4|4-screen
Mode 3 is identical to mode 2, except that the $08s and $20s bits affect the nametables:
|-
! $2000-$23FF
| colspan=4|R4
|-
! $2400-$27FF
| colspan=4|R5
|-
! $2800-$2BFF
| colspan=4|R6
|-
! $2C00-$2FFF
| colspan=4|R7
|}


If the $20s bit is clear, mode 3 is identical to mode 2.
===== Mode 2 =====
Mode 2 uses R6-R7 to select two ROM pages for horizontal or vertical mirroring. If using CIRAM, the LSB of each register applies.


If the $20s bit is set, CHR A10 is instead connected according to the $04s and $08s bits:
{| class="wikitable"
{| class="wikitable"
| 0 || horizontal mirroring || CHR A10 = PPU A11
! [$B003] & $F !!  $2 !!  $6 !!  $A !!  $E
|-
|-
| 4 || vertical mirroring || CHR A10 = PPU A10
! Mirroring
| vertical || horizontal || vertical || horizontal
|-
|-
| 8 || one-screen upper || CHR A10 = vcc
! $2000-$23FF
| R6 || R6 || R6 || R6
|-
|-
| 12 || one-screen lower || CHR A10 = gnd
! $2400-$27FF
| R7 || R6 || R7 || R6
|-
! $2800-$2BFF
| R6 || R7 || R6 || R7
|-
! $2C00-$2FFF
| R7 || R7 || R7 || R7
|}
|}
This is the same as the table in mode 0, but with the $04s bit inverted.


=== CHR Select 0…7 ($Dxxx, $Exxx) ===
===== Mode 3 =====
 
This mode is intended for ROM nametables ($B003:4 set) but the nametable banking is extended to 2 KiB pages by forcing the LSB as a 0 (even) or 1 (odd) in different configurations.
 
This can be used to spread 2 adjacent ROM pages each across a pair of nametables.
{| class="wikitable"
{| class="wikitable"
! PPU addressing mode !! 0 !! 1 !! 2 or 3
! [$B003] & $F !! $3 !! $7 !!  $B !! $F
|-
! Mirroring
| vertical pairs<br/> 2 KiB spread || horizontal pairs<br/> 2 KiB spread || vertical mirroring<br/> 1 KiB (odd only) || horizontal mirroring<br/> 1 KiB (even only)
|-
! $2000-$23FF
| R6 even || R6 even || R6 odd || R6 even
|-
|-
! Write to CPU address !! colspan=3|CHR banks affected
! $2400-$27FF
| R7 even || R6 odd  || R7 odd || R6 even
|-
|-
| $D000 || $0000-$03FF || $0000-$07FF || $0000-$03FF
! $2800-$2BFF
| R6 odd  || R7 even || R6 odd || R7 even
|-
|-
| $D001 || $0400-$07FF || $0800-$0FFF || $0400-$07FF
! $2C00-$2FFF
| R7 odd  || R7 odd  || R7 odd || R7 even
|-
|-
| $D002 || $0800-$0BFF || $1000-$17FF || $0800-$0BFF
! Mode 0 equivalent
| $4 || $0 || $C || $8
|}
 
The nametable configurations are redundant with [[#Mode 0|Mode 0]], but in a different order; however, the reuse of R6 and R7 as pattern banks makes mode 0 ineffective for ROM nametables.
 
===== Other =====
 
With $B003:5 clear, CHR/CIRAM A10 always directly uses the LSB of the register used to map that range, rather than having it overridden for mirroring control. (See nametable bank table above.)
 
This setting was intended to be used with a different PCB that would have connected PPU A10 directly to CHR A10, enabling 512 KiB CHR-ROM (with mode 1 having 2 KiB banks).
The actual behaviour here is a leftover consequence of being run on the wrong board:
 
{| class="wikitable"
! [$B003] & $F !! $0 !! $1 !! $2 !! $3 !! $4 !! $5 !! $6 !! $7 !! $8 !! $9 !! $A !! $B !! $C !! $D !! $E !! $F
|-
|-
| $D003 || $0C00-$0FFF || $1800-$1FFF || $0C00-$0FFF
! Mirroring
| H  || 4  || colspan=3|V    || 4  || colspan=3|H    || 4  || colspan=3|V    || 4  || colspan=2|H
|-
|-
| $E000 || $1000-$13FF || $2000-$23FF || $1000-$17FF
! $2000-$23FF
| R6 || R4 || R6 || R6 || R6 || R4 || R6 || R6 || R6 || R4 || R6 || R6 || R6 || R4 || R6 || R6
|-
|-
| $E001 || $1400-$17FF || $2400-$27FF || $1800-$1FFF
! $2400-$27FF
| R6 || R5 || R7 || R7 || R7 || R5 || R6 || R6 || R6 || R5 || R7 || R7 || R7 || R5 || R6 || R6
|-
|-
| $E002 || $1800-$1BFF || $2800-$2BFF || see previous
! $2800-$2BFF
| R7 || R6 || R6 || R6 || R6 || R6 || R7 || R7 || R7 || R6 || R6 || R6 || R6 || R6 || R7 || R7
|-
|-
| $E003 || $1C00-$1FFF || $2C00-$2FFF || see previous
! $2C00-$2FFF
| R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7 || R7
|}
|}


The $20s bit of $B003 controls whether 2 KiB banks pass PPU A10 through or instead present the full eight-bit latched value from the corresponding register.
Using ROM nametables on the hypothetical board mentioned above would transform all of the "H" layouts into "horizontal pairs 2 KiB spread", and all of the "V" and "4" layouts would have disjoint 256 KiB halves for the left two and right two nametables.


=== IRQ control ($F00x) ===
=== IRQ control ($F00x) ===


$F000:  IRQ Latch
For details on IRQ operation, see [[VRC IRQ]]s. Many VRC mappers use the same IRQ system.
$F001:  IRQ Control
$F002:  IRQ Acknowledge


Many VRC mappers use the same IRQ system.  For details on IRQ operation, see [[VRC_irq|VRC IRQs]].
The VRC6 IRQ can be used to count either CPU cycles, or scanlines as a multiple of CPU cycles.
 
        7  bit  0
        ---------
$F000: LLLL LLLL - IRQ Latch
$F001: .... .MEA - IRQ Control
  $F002: .... .... - IRQ Acknowledge
 
*L - reload value for latch
*M - mode (1=cycle, 0=scanline)
*E - enable IRQ
*A - acknowledge bit


=== Sound ($900x, $A00x, $B000-$B002) ===
=== Sound ($900x, $A00x, $B000-$B002) ===


For details on sound information, see [[VRC6_audio|VRC6 audio]].
For details on sound information, see [[VRC6_audio|VRC6 audio]].
== Revisions ==
Three revisions of the VRC6 chip are known to exist:
* 053328 - pin 1 is GND
* 053329 - pin 1 appears to be an input
* 053330 - based on the SLA7340 CMOS gate array, pin 1 is GND
== References ==
* Official VRC6 documentation: http://www.assemblergames.com/forums/showthread.php?48390-Several-Famicom%28NES%29-misc-dev-documents-from-Nintendo-and-Konami
* Naruko's explanation of the $B003 register according to the VRC6 documentation: http://forums.nesdev.org/viewtopic.php?f=11&t=10628
*[http://nesdev.org/vrcvi.txt VRCVI Chip Info] by Kevin Horton (audio only)
*[http://nesdev.org/vrc6-j.txt VRCVI] by goroh (sound info is inaccurate)
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate.
*[//forums.nesdev.org/viewtopic.php?t=11028 VRC6 mirroring test ROM]

Latest revision as of 14:54, 18 July 2022

VRC6
Company Konami
Games 3 in NesCartDB
Complexity ASIC
Boards 351951, 351949A
Pinout VRC6 pinout
PRG ROM capacity 256K
PRG ROM window 16K + 8K
PRG RAM capacity 8K
PRG RAM window 8K
CHR capacity 256K
CHR window 1K
Nametable mirroring H, V, or 1, switchable
Bus conflicts No
IRQ Yes
Audio Yes
iNES mappers 024, 026

The Konami's VRC6 ASIC mapper comes in two variants:

  • VRC6a - iNES Mapper 024 used for Akumajou Densetsu (Konami PCB 351951).
  • VRC6b - iNES Mapper 026 used for Madara and Esper Dream 2 (Konami PCB 351949A).

The difference between the two variants switches the A0 and A1 lines. The registers described on this page are for mapper 24, but for mapper 26 the register addresses must be adjusted ($x001 becomes $x002 and vice versa).

See VRC6 pinout for chip pinout.


Banks

CPU

  • $6000-$7FFF: 8 KB PRG-RAM bank, fixed
  • $8000-$BFFF: 16 KB switchable PRG ROM bank
  • $C000-$DFFF: 8 KB switchable PRG ROM bank
  • $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank

PPU

  • $0000-$03FF: 1 KB switchable CHR ROM bank
  • $0400-$07FF: 1 KB switchable CHR ROM bank
  • $0800-$0BFF: 1 KB switchable CHR ROM bank
  • $0C00-$0FFF: 1 KB switchable CHR ROM bank
  • $1000-$13FF: 1 KB switchable CHR ROM bank
  • $1400-$17FF: 1 KB switchable CHR ROM bank
  • $1800-$1BFF: 1 KB switchable CHR ROM bank
  • $1C00-$1FFF: 1 KB switchable CHR ROM bank

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

The addresses described here are for mapper 24. The registers for mapper 26 can be found by swapping bits 0 and 1 of the address. 

    variant   lines     registers                       Mapper Number
    =================================================================
    VRC6a:    A0, A1    $x000, $x001, $x002, $x003      024
    VRC6b:    A1, A0    $x000, $x002, $x001, $x003      026

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM bank at $8000-$BFFF

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM bank at $C000-$DFFF

PPU Banking Style ($B003)

7  bit  0
---------
W.PN MMDD
| || ||||
| || ||++- PPU banking mode; see below
| || ++--- Mirroring varies by banking mode, see below
| |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
| +------- CHR A10 is 1: subject to further rules 0: according to the latched value
+--------- PRG RAM enable

The VRC6 supports the use of a larger RAM to provide more nametables. However, the three commercial VRC6 games neither provided extra nametable RAM, nor used ROM nametables. As a result these games only ever write the values $20, $24, $28, $2C, $A0, $A4, $A8, and $AC to this register.

CIRAM A10 is always connected to CHR A10, and bit 5 affects the behaviour of this signal (see below for details). The commercial games always left this bit set.

CHR Select 0…7 ($Dxxx, $Exxx)

For brevity, we refer to the registers at $D000 through $D003 and $E000 through $E003 as R0 through R7.

The lower 3 bits of the $B003 register affect where the registers are used:

[$B003] & $03 → 0 1 2 or 3
CHR bank Register used
$0000-$03FF R0 R0 R0
$0400-$07FF R1 R1
$0800-$0BFF R2 R1 R2
$0C00-$0FFF R3 R3
$1000-$13FF R4 R2 R4
$1400-$17FF R5
$1800-$1BFF R6 R3 R5
$1C00-$1FFF R7
[$B003] & $07 → 0, 6, or 7 1 or 5 2, 3, or 4
Nametable bank Register used
$2000-$23FF R6 R4 R6
$2400-$27FF R6 R5 R7
$2800-$2BFF R7 R6 R6
$2C00-$2FFF R7 R7 R7

When bit 5 of $B003 is clear, CHR/CIRAM A10 will be controlled directly by the register LSB, causing 2 KiB banks to have duplicate 1 KiB halves. Existing Konami games did not use this configuration. This was intended for a different PCB (never used) where PPU A10 directly controls CHR A10 instead, permitting 512 KiB of CHR-ROM.

When bit 5 of $B003 is set, 2 KiB pattern table banks pass PPU A10 through (ignoring the LSB of the register). Nametables apply different rules at the same time: see below.

Mirroring

With $B003:5 set, there are four different modes corresponding to $B003 & 3 that each have 4 nametable mirroring settings. Only mode 0 was used by Konami's commercial games.

Mode 0
[$B003] & $F $0 $4 $8 $C
Mirroring vertical horizontal 1-screen A 1-screen B
CIRAM A10 PPU A10 PPU A11 Ground (0) Vcc (1)

This mode was not intended for use with ROM nametables ($B003:4 set), because it overrides the LSB of the nametable registers with the signal intended for CIRAM A10. Because R6 and R7 are already in use to control the pattern banks, this is not very suitable if combined with ROM nametables (Mode 3 is designed for that instead).

[$B003] & $F $0 $4 $8 $C
Mirroring horizontal pairs
2 KiB spread		 vertical pairs
2 KiB spread		 horizontal mirroring
1 KiB (even only)		 vertical mirroring
1 KiB (odd only)
$2000-$23FF R6 even R6 even R6 even R6 odd
$2400-$27FF R6 odd R7 even R6 even R7 odd
$2800-$2BFF R7 even R6 odd R7 even R6 odd
$2C00-$2FFF R7 odd R7 odd R7 even R7 odd
Mode 3 equivalent $7 $3 $F $B
Mode 1

Mode 1 uses R4-R7 to directly control 4-screen mapping. This is very effective with ROM nametables ($B003:4 set), but the LSB of each register still applies when using CIRAM.

[$B003] & $F $1 $5 $9 $D
Mirroring 4-screen
$2000-$23FF R4
$2400-$27FF R5
$2800-$2BFF R6
$2C00-$2FFF R7
Mode 2

Mode 2 uses R6-R7 to select two ROM pages for horizontal or vertical mirroring. If using CIRAM, the LSB of each register applies.

[$B003] & $F $2 $6 $A $E
Mirroring vertical horizontal vertical horizontal
$2000-$23FF R6 R6 R6 R6
$2400-$27FF R7 R6 R7 R6
$2800-$2BFF R6 R7 R6 R7
$2C00-$2FFF R7 R7 R7 R7
Mode 3

This mode is intended for ROM nametables ($B003:4 set) but the nametable banking is extended to 2 KiB pages by forcing the LSB as a 0 (even) or 1 (odd) in different configurations.

This can be used to spread 2 adjacent ROM pages each across a pair of nametables.

[$B003] & $F $3 $7 $B $F
Mirroring vertical pairs
2 KiB spread		 horizontal pairs
2 KiB spread		 vertical mirroring
1 KiB (odd only)		 horizontal mirroring
1 KiB (even only)
$2000-$23FF R6 even R6 even R6 odd R6 even
$2400-$27FF R7 even R6 odd R7 odd R6 even
$2800-$2BFF R6 odd R7 even R6 odd R7 even
$2C00-$2FFF R7 odd R7 odd R7 odd R7 even
Mode 0 equivalent $4 $0 $C $8

The nametable configurations are redundant with Mode 0, but in a different order; however, the reuse of R6 and R7 as pattern banks makes mode 0 ineffective for ROM nametables.

Other

With $B003:5 clear, CHR/CIRAM A10 always directly uses the LSB of the register used to map that range, rather than having it overridden for mirroring control. (See nametable bank table above.)

This setting was intended to be used with a different PCB that would have connected PPU A10 directly to CHR A10, enabling 512 KiB CHR-ROM (with mode 1 having 2 KiB banks). The actual behaviour here is a leftover consequence of being run on the wrong board:

[$B003] & $F $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
Mirroring H 4 V 4 H 4 V 4 H
$2000-$23FF R6 R4 R6 R6 R6 R4 R6 R6 R6 R4 R6 R6 R6 R4 R6 R6
$2400-$27FF R6 R5 R7 R7 R7 R5 R6 R6 R6 R5 R7 R7 R7 R5 R6 R6
$2800-$2BFF R7 R6 R6 R6 R6 R6 R7 R7 R7 R6 R6 R6 R6 R6 R7 R7
$2C00-$2FFF R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7 R7

Using ROM nametables on the hypothetical board mentioned above would transform all of the "H" layouts into "horizontal pairs 2 KiB spread", and all of the "V" and "4" layouts would have disjoint 256 KiB halves for the left two and right two nametables.

IRQ control ($F00x)

For details on IRQ operation, see VRC IRQs. Many VRC mappers use the same IRQ system.

The VRC6 IRQ can be used to count either CPU cycles, or scanlines as a multiple of CPU cycles. 

       7  bit  0
       ---------
$F000: LLLL LLLL - IRQ Latch
$F001: .... .MEA - IRQ Control
$F002: .... .... - IRQ Acknowledge
  • L - reload value for latch
  • M - mode (1=cycle, 0=scanline)
  • E - enable IRQ
  • A - acknowledge bit

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.

Revisions

Three revisions of the VRC6 chip are known to exist:

  • 053328 - pin 1 is GND
  • 053329 - pin 1 appears to be an input
  • 053330 - based on the SLA7340 CMOS gate array, pin 1 is GND

References

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