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| [[Category:ASIC mappers]] | | #REDIRECT [[VRC2 and VRC4]] |
| The Konami VRC2 is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]].
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| __TOC__
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| == Overview ==
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| * PRG ROM size: Up to 256 KB
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| * PRG ROM bank size: 8 KiB
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| * PRG RAM: One bit or 8 KiB
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| * CHR bank size: 1 KiB
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| * Nametable [[mirroring]]: Controlled by mapper
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| * Subject to [[bus conflict]]s: No
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| The Konami VRC2 is almost identical to the [[VRC4|VRC4]], but a bit more limited.
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| See [[VRC2 pinout]] for chip pinout.
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| == Banks ==
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| * CPU $6000-$6FFF: 1 bit unknown latch, or
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| * CPU $6000-$7FFF: optional 8 KiB RAM
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| * CPU $8000-$9FFF: 8 KiB switchable PRG ROM bank
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| * CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
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| * CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last 16 KiB
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| * PPU $0000-$03FF: 1 KiB switchable CHR bank
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| * PPU $0400-$07FF: 1 KiB switchable CHR bank
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| * PPU $0800-$0BFF: 1 KiB switchable CHR bank
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| * PPU $0C00-$0FFF: 1 KiB switchable CHR bank
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| * PPU $1000-$13FF: 1 KiB switchable CHR bank
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| * PPU $1400-$17FF: 1 KiB switchable CHR bank
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| * PPU $1800-$1BFF: 1 KiB switchable CHR bank
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| * PPU $1C00-$1FFF: 1 KiB switchable CHR bank
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| == Revisions ==
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| This mapper had two known revisions: VRC2a and VRC2b. Both revisions uses Address lines A0, A1, and A12-A15 for registers, however VRC2a has A0 and A1 "backwards" from the norm. Address $x001 on VRC2b would be $x002 on VRC2a, and $x002 on VRC2b would be $x001 on VRC2a.
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| Additionally, VRC2a has 7-bit wide CHR registers, whereas VRC2b has 8-bit wide CHR registers.
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| The two wiring variants correspond to iNES mappers [[INES Mapper 022|22]] and [[INES Mapper 023|23]].
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| A third variant (similar to VRC2a but with full-width CHR registers and PRG-RAM) is canonically emulated as using the VRC4, and it's assigned to [[iNES Mapper 025|mapper 25]].
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| This page lists registers as they are in the VRC2b variant. For VRC2a registers, reverse A0 and A1 lines.
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| == Registers ==
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| === PRG Select 0 ($8000, $8001, $8002, $8003) ===
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| 7 bit 0
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| ---------
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| ...P PPPP
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| + ++++- Select 8 KB PRG bank at $8000
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| === PRG Select 1 ($A000, $A001, $A002, $A003) ===
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| 7 bit 0
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| ---------
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| ...P PPPP
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| + ++++- Select 8 KB PRG bank at $A000
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| === Mirroring Control ($9000, $9001, $9002, $9003) ===
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| 7 bit 0
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| ---------
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| .... ..MM
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| ++- [[Mirroring]] (0: vertical; 1: horizontal;
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| 2: one-screen, lower bank; 3: one-screen, upper bank;)
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| === CHR Select 0 ($B000 + $B001) ===
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| $B000 $B001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0000
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 1 ($B002 + $B003) ===
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| $B002 $B003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0400
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 2 ($C000 + $C001) ===
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| $C000 $C001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0800
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 3 ($C002 + $C003) ===
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| $C002 $C003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $0C00
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 4 ($D000 + $D001) ===
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| $D000 $D001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1000
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 5 ($D002 + $D003) ===
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| $D002 $D003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1400
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 6 ($E000 + $E001) ===
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| $E000 $E001
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1800
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === CHR Select 7 ($E002 + $E003) ===
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| $E002 $E003
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL .... HHHH
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| |||| ||||
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| |||| ++++- High 4-bits of 1 KB CHR bank at PPU $1C00
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| ++++-------------- Low 4-bits
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| Note: On VRC2a, the low bit is ignored (right shift value by 1)
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| === Unknown Latch ($6000-$6FFF) ===
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| 7 bit 0
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| ---------
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| .... ...L
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| +- 1-bit latch value (r/w)
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| On boards that lack PRG RAM, this register bit serves an unknown purpose.
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| Many VRC2 games such as Contra (J) and Ganbare Goemon 2 (J) write to the lowest bit of $6000, and expect to be able to read it back. Returning either open bus or 0x00 will not work, and the games will lock almost immediately after execution begins.
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| Emulators that use the same VRC4 core (and its 8KB of PRG RAM) for VRC2 emulation will have the effect simulated for them. However, most VRC2 boards do not contain any RAM.
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| Reads from $6000-6FFF return open bus for the top 7 bits; the LSB agrees with the last value written. e.g. both LDA $6100 and LDA $6000 will return $60|latch. $7000-7FFF returns only open bus, ignoring the latch.
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