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| UNIF MAPR '''COOLBOY''' describes a mapper designed for MMC3 multicarts. Unlike almost all other mappers, it is currently being manufactured. (Search for "COOLBOY" on eBay or AliExpress).
| | #REDIRECT [[NES 2.0 Mapper 268]] |
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| It adds four extra registers in lieu of (in addition to?) the normal PRG-RAM, gated by the normal MMC3 PRG-RAM access. FCEUX claims that all four of these registers are cleared on power up and reset.
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| == Registers ==
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| Note: Much like with [[iNES Mapper 037|Nintendo's]] first-party [[iNES Mapper 047|MMC3 multicarts]], you MUST enable writes to the MMC3's PRG RAM to write to these registers.
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| Mask: $E003
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| === $6000 ===
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| 7 bit 0
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| ---- ----
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| ABCC DEEE
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| |||| |+++-- PRG offset (PRG A19, A18, A17)
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| |||| +----- Alternate CHR A17
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| ||++------- PRG offset (PRG A24, A23)
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| |+--------- PRG mask (PRG A17 from 0: MMC3; 1: offset)
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| +---------- CHR mask (CHR A17 from 0: MMC3; 1: alternate)
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| === $6001 ===
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| 7 bit 0
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| ---- ----
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| GHIJ KKLx
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| |||| ||+--- GNROM mode bank PRG size (1: 32 KiB bank, PRG A14=CPU A14; 0: 16 KiB bank, PRG A14=offset A14)
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| |||+-++---- PRG offset (in order: PRG A20, A22, A21)
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| ||+-------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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| |+--------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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| +---------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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| === $6002 ===
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| 7 bit 0
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| ---- ----
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| xxxx MMMM
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| ++++-- CHR offset for GNROM mode (CHR A16, A15, A14, A13)
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| === $6003 ===
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| 7 bit 0
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| ---- ----
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| NPxP QQRx
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| || | +++--- PRG offset for GNROM mode (PRG A16, A15, A14)
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| || +------- 1: GNROM mode; 0: MMC3 mode
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| |+-+------- Banking mode
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| |+--------- "Weird mode"
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| +---------- Lockout (prevent further writes to these four registers, only works when mode = $00 or $40.)
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| == Register interpretation ==
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| === Banking mode = $00 ===
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| “Normal” oversize MMC3 mode.
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| PRG offset is expressed as a multiple of 128 KiB = CCKKJEEE
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| PRG mask controls whether each of A17 through A20 connect to MMC3 or to the above JEEE LSBs.
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| CHR A17 is controlled by MMC3 and the two bits in register $6000.
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| Lockout works in this mode.
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| === Banking mode = $10 ===
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| “Normal” GNROM mode.
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| When in 32 KiB mode (see $6001.1), PRG offset as a multiple of 32 KiB is CCKKJEEEQQ.
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| When in 16 KiB mode, PRG offset as a multiple of 16 KiB is CCKKJEEEQQR.
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| PRG mask registers STILL AFFECT THIS MODE, allowing weird splicing of MMC3 banking (granularity of 128 KiB) overlaying GNROM-style banking.
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| CHR offset, as a multiple of 8 KiB is DMMMM. BUT the CHR A17 multiplexer still works, so the MSB of the CHR banks still can come from the MMC3.
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| Lockout DOES NOT work in this mode.
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| === Banking mode = $40 ===
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| “Weird” MMC3 mode.
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| If MMC3 PRG ROM bank mode is "normal" (8+8+16F), then the PRG banks at 0xC000 and 0xE000 are fixed to 8 KiB bank 0, instead of 0xFE and 0xFF. Supposedly there is no effect ''at all'' when MMC3 PRG ROM bank mode is inverted (8F+8+8+8F).
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| The second half of each of the 2 KiB CHR banks is replaced with bank 0, and the LSB of MMC3 registers 0 and 1 work (instead of being replaced by PPU A10).
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| Otherwise, behaves as “normal” MMC3 mode above.
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| === Banking mode = $50 ===
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| “Weird” GNROM-ish mode.
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| Combine the rules mentioned for PRG above for “Normal” GNROM mode with “Weird” MMC3 mode.
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| The 1 KiB slices of the MMC3 2 KiB CHR banks that would have been forced to be bank 0 in “weird” MMC3 mode have their MSB (CHR A17) line set to 0.
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| Lockout DOES NOT work in this mode.
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