Sunsoft 1 pinout: Difference between revisions
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m (switch to using CPU/PRG and PPU/CHR for extra clarity, also boldified deltas) |
(italics for Fantasy Zone) |
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Sunsoft-1: 16 pin 0.3" PDIP | [[Category:Pinouts]]Sunsoft-1: 16 pin 0.3" PDIP (canonically [[iNES Mapper 184|mapper 184]]) | ||
.---\/---. | |||
(f) PPU A12 -> |01 16| -- +5V | |||
(f) M2 -> |02 15| -> CHR A12 (r) | |||
( | (fr) /ROMSEL -> |03 14| -> CHR A14 (r) | ||
( | (fr) CPU A13 -> |04 13| -> CHR A13 (r) | ||
( | (fr) CPU A14 -> |05 12| <- CPU RnW (f) | ||
( | (fr) CPU D5 -> |06 11| <- CPU D0 (fr) | ||
( | (fr) CPU D4 -> |07 10| <- CPU D1 (fr) | ||
GND -- |08 09| <- CPU D2 (fr) | |||
`--------' | |||
NOTE: D6 is NOT connected | NOTE: D6 is NOT connected. Games simply always write to the mapper with D6 set. The wiring for ''Fantasy Zone'' implies the virtual D6 is treated as though it were connected to +5V always. | ||
Alternative wiring for Fantasy Zone: | Alternative wiring for ''Fantasy Zone'': | ||
.---\/---. | |||
(f) '''CPU A14''' -> |01 16| -- +5V | |||
(f) M2 -> |02 15| -> '''PRG A14''' (r) | |||
( | (fr) /ROMSEL -> |03 14| -> '''PRG A16''' (r) | ||
( | (fr) CPU A13 -> |04 13| -> '''PRG A15''' (r) | ||
(f) CPU A14 -> |05 12| <- CPU RnW (f) | |||
'''+5V''' -> |06 11| <- CPU D0 (fr) | |||
'''+5V''' -> |07 10| <- CPU D1 (fr) | |||
GND -- |08 09| <- CPU D2 (fr) | |||
`--------' |
Latest revision as of 23:55, 12 February 2023
Sunsoft-1: 16 pin 0.3" PDIP (canonically mapper 184)
.---\/---. (f) PPU A12 -> |01 16| -- +5V (f) M2 -> |02 15| -> CHR A12 (r) (fr) /ROMSEL -> |03 14| -> CHR A14 (r) (fr) CPU A13 -> |04 13| -> CHR A13 (r) (fr) CPU A14 -> |05 12| <- CPU RnW (f) (fr) CPU D5 -> |06 11| <- CPU D0 (fr) (fr) CPU D4 -> |07 10| <- CPU D1 (fr) GND -- |08 09| <- CPU D2 (fr) `--------'
NOTE: D6 is NOT connected. Games simply always write to the mapper with D6 set. The wiring for Fantasy Zone implies the virtual D6 is treated as though it were connected to +5V always.
Alternative wiring for Fantasy Zone:
.---\/---. (f) CPU A14 -> |01 16| -- +5V (f) M2 -> |02 15| -> PRG A14 (r) (fr) /ROMSEL -> |03 14| -> PRG A16 (r) (fr) CPU A13 -> |04 13| -> PRG A15 (r) (f) CPU A14 -> |05 12| <- CPU RnW (f) +5V -> |06 11| <- CPU D0 (fr) +5V -> |07 10| <- CPU D1 (fr) GND -- |08 09| <- CPU D2 (fr) `--------'