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| '''SXROM''' (HVC-SXROM) is one of the less common boards within the [[SxROM]] subset. Like other SxROM boards, SXROM uses the [[MMC1|Nintendo MMC1]] ASIC, but because it always uses CHR RAM, it uses three spare CHR address lines to select between two 256 kb PRG ROM banks, and four 8kb PRG RAM banks letting the program access up to 512 kb of PRG ROM and 32 KB of PRG RAM at once. To keep things simple, it is in some sort a combination of [[SUROM]] and [[SOROM]].
| | #REDIRECT [[SxROM]] |
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| It should be noted that only Japanese HVC-SXROM boards have ever been produced, so this board has no 72-pin "NES-SXROM" counterpart.
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| == Overview ==
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| * PRG ROM size: 128, 256 or 512 KB (DIP-28/32 Nintendo pinout)
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| * PRG ROM bank size: 16 KB or 32 KB
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| * PRG RAM: 32 KB + battery
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| * CHR capacity: 8 KB RAM
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| * CHR bank size: 8 KB or 4 KB
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| * Nametable [[mirroring]]: Controlled by mapper
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| * Subject to [[bus conflict]]s: No
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| == Solder pad config ==
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| * PRG RAM retaining data : 'SL1' disconnected, Battery, D1, D2, R1 and R2 present.
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| * PRG RAM not retaining data : 'SL1' connected, leave slots for Battery, D1, D2, R1 and R2 free.
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| == Hardware ==
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| This particular board uses a 74HCU04 (hex inverter) to invert and buffer the enable signals from the MMC1, and that inverter is also battery backed just like the SRAM, so that the SRAM protection on power down is greatly improved (however, the current drawn by the battery is significantly supperior to other cartridges, so the battery may run out faster).
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| == Registers ==
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| The behavior of this board differs from that of a typical MMC1 board in the use of the upper CHR address lines:
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| === CHR bank 0 (internal, $A000-$BFFF) ===
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| 4bit0
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| -----
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| PSSxC
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| ||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
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| |++--- Select 8 KB PRG RAM bank
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| +----- Select 256 KB PRG ROM bank
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| === CHR bank 1 (internal, $C000-$DFFF) ===
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| 4bit0
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| -----
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| PSSxC
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| ||| +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
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| |++--- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
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| +----- Select 256 KB PRG ROM bank (ignored in 8 KB mode)
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| Note: In 4KB CHR bank mode, the <code>P</code> and <code>S</code> bits in both CHR bank registers must be set to the same value, or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]].
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