Namcot 108 family pinout: Difference between revisions
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m (Add the specifics of the differences in pinout layout across mappers #s.) |
m (switch to using CPU/PRG and PPU/CHR for extra clarity) |
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| Line 2: | Line 2: | ||
.--\/--. | .--\/--. | ||
(n) | (n) CPU A14 -> |01 28| -> PRG A15 (r) | ||
(s) | (s) CPU A0 -> |02 27| -> PRG A14 (r) | ||
(s) | (s) CPU D5 -> |03 26| <- M2 (n) | ||
(s) | (s) CPU D0 -> |04 25| -> PRG A13 (r) | ||
(s) | (s) CPU D4 -> |05 24| <- CPU A13 (n) | ||
(s) | (s) CPU D1 -> |06 23| -> PRG A16 (r) | ||
Gnd -- |07 22| -> PRG /CE (r) | Gnd -- |07 22| -> PRG /CE (r) | ||
(s) | (s) CPU D3 -> |08 21| -- +5V | ||
(s) | (s) CPU D2 -> |09 20| -> CHR A13 (r) | ||
(n) / | (n) /ROMSEL -> |10 19| -> CHR A11 (r) | ||
(n) R/W -> |11 18| -> CHR A10 (r) | (n) R/W -> |11 18| -> CHR A10 (r) | ||
(r) CHR A15 <- |12 17| <- | (r) CHR A15 <- |12 17| <- PPU A10 (n) | ||
(r) CHR A14 <- |13 16| <- | (r) CHR A14 <- |13 16| <- PPU A11 (n) | ||
(r) CHR A12 <- |14 15| <- | (r) CHR A12 <- |14 15| <- PPU A12 (n) | ||
`------' | `------' | ||
| Line 23: | Line 23: | ||
[[INES Mapper 076|Mapper 76]]: | [[INES Mapper 076|Mapper 76]]: | ||
(s) | (s) CPU D2 -> |09 20| -> CHR '''A14''' (r) | ||
(n) / | (n) /ROMSEL -> |10 19| -> CHR '''A12''' (r) | ||
(n) R/W -> |11 18| -> CHR '''A11''' (r) | (n) R/W -> |11 18| -> CHR '''A11''' (r) | ||
(r) CHR '''A16''' <- |12 17| <- | (r) CHR '''A16''' <- |12 17| <- PPU '''A11''' (n) | ||
(r) CHR '''A15''' <- |13 16| <- | (r) CHR '''A15''' <- |13 16| <- PPU '''A12''' (n) | ||
(r) CHR '''A13''' <- |14 15| <- '''+5V''' | (r) CHR '''A13''' <- |14 15| <- '''+5V''' | ||
`------' | `------' | ||
'''(n) | '''(n) PPU A10 -> CHR A10 (r)''' | ||
Mappers [[INES Mapper 088|88]] and [[INES Mapper 154|154]] connect (n) | Mappers [[INES Mapper 088|88]] and [[INES Mapper 154|154]] connect (n) PPU A12 -> CHR A16 (r), skipping the mapper IC altogether. | ||
[[INES Mapper 095|Mapper 95]]: | [[INES Mapper 095|Mapper 95]]: | ||
'''(n) CIRAM A10''' <- |12 17| <- | '''(n) CIRAM A10''' <- |12 17| <- PPU A10 (n) | ||
(r) CHR A14 <- |13 16| <- | (r) CHR A14 <- |13 16| <- PPU A11 (n) | ||
(r) CHR A12 <- |14 15| <- | (r) CHR A12 <- |14 15| <- PPU A12 (n) | ||
`------' | `------' | ||
Revision as of 23:36, 23 July 2012
Namcot 108, Namcot 109, Namcot 118, Namcot 119: 28-pin shrink PDIP (Canonically mapper 206).
.--\/--.
(n) CPU A14 -> |01 28| -> PRG A15 (r)
(s) CPU A0 -> |02 27| -> PRG A14 (r)
(s) CPU D5 -> |03 26| <- M2 (n)
(s) CPU D0 -> |04 25| -> PRG A13 (r)
(s) CPU D4 -> |05 24| <- CPU A13 (n)
(s) CPU D1 -> |06 23| -> PRG A16 (r)
Gnd -- |07 22| -> PRG /CE (r)
(s) CPU D3 -> |08 21| -- +5V
(s) CPU D2 -> |09 20| -> CHR A13 (r)
(n) /ROMSEL -> |10 19| -> CHR A11 (r)
(n) R/W -> |11 18| -> CHR A10 (r)
(r) CHR A15 <- |12 17| <- PPU A10 (n)
(r) CHR A14 <- |13 16| <- PPU A11 (n)
(r) CHR A12 <- |14 15| <- PPU A12 (n)
`------'
No behavioral differences are known between the 4 different part numbers; several games were released on the same board with identical code and different mapper ICs.
Many boards (and thus iNES mappers) redefined parts of the pinout for various extensions, mostly to increase the amount of addressable CHR ROM.
(s) CPU D2 -> |09 20| -> CHR A14 (r)
(n) /ROMSEL -> |10 19| -> CHR A12 (r)
(n) R/W -> |11 18| -> CHR A11 (r)
(r) CHR A16 <- |12 17| <- PPU A11 (n)
(r) CHR A15 <- |13 16| <- PPU A12 (n)
(r) CHR A13 <- |14 15| <- +5V
`------'
(n) PPU A10 -> CHR A10 (r)
Mappers 88 and 154 connect (n) PPU A12 -> CHR A16 (r), skipping the mapper IC altogether.
(n) CIRAM A10 <- |12 17| <- PPU A10 (n)
(r) CHR A14 <- |13 16| <- PPU A11 (n)
(r) CHR A12 <- |14 15| <- PPU A12 (n)
`------'
