NES 2.0 Mapper 287: Difference between revisions
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NewRisingSun (talk | contribs) (Created page with "Category:Multicart mappersCategory:MMC3-like mappersNES 2.0 Mapper 287 is used for at least two 4-in-1 multicarts (411120-C, 811120-C). Its UNIF board name is '''BMC-4...") |
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[[Category:Multicart mappers]][[Category:MMC3-like mappers]]NES 2.0 Mapper 287 is used for at least two 4-in-1 multicarts (411120-C, 811120-C). Its UNIF board | {{DEFAULTSORT:287}}[[Category:Multicart mappers]][[Category:MMC3-like mappers]]NES 2.0 Mapper 287 is used for at least two 4-in-1 multicarts (411120-C, 811120-C). Its UNIF board names are '''BMC-411120-C''' and '''BMC-K-3088'''. The former has a DIP switch or jumper with a 0/1 setting. | ||
== | ==Outer Bank Register ($6000-$7FFF, write)== | ||
Mask: | Mask: $E000 | ||
D~7654 3210 | |||
--------- | |||
..II MmOO | |||
|| |+++- Select 128 KiB Outer PRG-ROM/CHR-ROM bank regardless of banking mode | |||
|| |+--- If DIP Switch ==1: Same function as Bit 3 | |||
|| ++--- Select PRG Banking Mode | |||
|| 0: MMC3 Inner Bank, 128 KiB Outer Bank | |||
|| 1: 32 KiB Inner Bank (Bits 0-1) and 128 KiB Outer Bank | |||
++------ Select 32 KiB inner PRG-ROM bank at CPU $8000-$FFFF if Bit 3==0 | |||
==MMC3-compatible registers ($8000-$FFFF, write)== | ==MMC3-compatible registers ($8000-$FFFF, write)== | ||
| Line 18: | Line 18: | ||
$8000, $8001, $A000, $A001, $C000, $C001, $E000, $E001: As normal [[MMC3]]. | $8000, $8001, $A000, $A001, $C000, $C001, $E000, $E001: As normal [[MMC3]]. | ||
=Notes= | |||
* Because the outer bank register is connected to where WRAM would normally be, WRAM needs to be enabled via bit 7 of MMC3 register $A001 before accessing the outer bank register. | |||
Latest revision as of 06:38, 26 May 2020
NES 2.0 Mapper 287 is used for at least two 4-in-1 multicarts (411120-C, 811120-C). Its UNIF board names are BMC-411120-C and BMC-K-3088. The former has a DIP switch or jumper with a 0/1 setting.
Outer Bank Register ($6000-$7FFF, write)
Mask: $E000
D~7654 3210
---------
..II MmOO
|| |+++- Select 128 KiB Outer PRG-ROM/CHR-ROM bank regardless of banking mode
|| |+--- If DIP Switch ==1: Same function as Bit 3
|| ++--- Select PRG Banking Mode
|| 0: MMC3 Inner Bank, 128 KiB Outer Bank
|| 1: 32 KiB Inner Bank (Bits 0-1) and 128 KiB Outer Bank
++------ Select 32 KiB inner PRG-ROM bank at CPU $8000-$FFFF if Bit 3==0
MMC3-compatible registers ($8000-$FFFF, write)
Mask: $E001 $8000, $8001, $A000, $A001, $C000, $C001, $E000, $E001: As normal MMC3.
Notes
- Because the outer bank register is connected to where WRAM would normally be, WRAM needs to be enabled via bit 7 of MMC3 register $A001 before accessing the outer bank register.
