MMC2 pinout: Difference between revisions

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MMC2 Chip:    (40/42 pin shrink-DIP)
[[MMC2]] Chip:    (40/42 pin shrink-DIP)


Modern revisions of the chip are labelled MMC2-L and are 42 pin instead of 40 pin.
Later revisions of the chip are labelled MMC2-L and are 42 pin instead of 40 pin.


                                  .----\/----.
                  .--\/--.
                            GND  - |XX     XX| -  +5V
          GND  - |XX XX| -  +5V
                            M2 -> |01     40| -  +5V
  (n)      M2 -> |01 40| -  +5V
                    PRG A14 (n) -> |02     39| -  GND
  (n) CPU A14 -> |02 39| -  GND
                    PRG A13 (n) -> |03     38| -> CIRAM A10 (n)
  (n) CPU A13 -> |03 38| -> CIRAM A10 (n)
                    PRG A15 (r) <- |04     37| -> CHR A15 (r)
  (r) PRG A15 <- |04 37| -> CHR A15 (r)
                    PRG A14 (r) <- |05     36| -> CHR A12 (r)
  (r) PRG A14 <- |05 36| -> CHR A12 (r)
                    PRG A12 (s) -> |06     35| -> CHR A14 (r)
  (rn) CPU A12 -> |06 35| -> CHR A14 (r)
                    PRG A13 (r) <- |07     34| <- CHR A12 (n)
  (r) PRG A13 <- |07 34| <- PPU A12 (n)
                    PRG A16 (r) <- |08     33| -> CHR A13 (r)
  (r) PRG A16 <- |08 33| -> CHR A13 (r)
                    PRG /CE (r) <- |09     32| -> CHR A16 (r)
  (r) PRG /CE <- |09 32| -> CHR A16 (r)
                    PRG D4 (s) -> |10     31| <- CHR A8 (s)
  (rn) CPU  D4 -> |10 31| <- PPU  A8 (rn)
                    PRG D3 (s) -> |11     30| <- CHR A5 (s)
  (rn) CPU  D3 -> |11 30| <- PPU  A5 (rn)
                    PRG D0 (s) -> |12     29| <- CHR A9 (s)
  (rn) CPU  D0 -> |12 29| <- PPU  A9 (rn)
                    PRG D1 (s) -> |13     28| <- CHR A4 (s)
  (rn) CPU  D1 -> |13 28| <- PPU  A4 (rn)
                    PRG D2 (s) -> |14     27| <- CHR A11 (s)
  (rn) CPU  D2 -> |14 27| <- PPU A11 (rn)
                    PRG R/W (n) -> |15     26| <- CHR A3 (s)
  (n) CPU R/W -> |15 26| <- PPU  A3 (rn)
                    PRG /CE (n) -> |16     25| <- CHR A7 (s)
  (n) /ROMSEL -> |16 25| <- PPU  A7 (rn)
                    CHR /RD (s) -> |17     24| <- CHR A2 (s)
  (rn) PPU /RD -> |17 24| <- PPU  A2 (rn)
                    CHR A0 (s) -> |18     23| <- CHR A10 (s)
  (rn) PPU  A0 -> |18 23| <- PPU A10 (rn)
                    CHR A6 (s) -> |19     22| <- CHR A1 (s)
  (rn) PPU  A6 -> |19 22| <- PPU  A1 (rn)
                            GND  - |20     21| <- CHR /CE (s)
          GND  - |20 21| <- PPU A13 (rn)
                                  `----------'
                  `------'
(r) - this pin connects to the ROM chips
(n) - this pin connects to the NES connector


(r) - this pin connects to the ROM chips only
[[Category:Pinouts]]
(n) - this pin connects to the NES connector only
(s) - this pin is shared with the NES connector and ROM chips
(w) - this pin connects to the WRAM only

Latest revision as of 07:39, 22 November 2013

MMC2 Chip: (40/42 pin shrink-DIP)

Later revisions of the chip are labelled MMC2-L and are 42 pin instead of 40 pin. 

                 .--\/--.
          GND  - |XX  XX| -  +5V
  (n)      M2 -> |01  40| -  +5V
  (n) CPU A14 -> |02  39| -  GND
  (n) CPU A13 -> |03  38| -> CIRAM A10 (n)
  (r) PRG A15 <- |04  37| -> CHR A15 (r)
  (r) PRG A14 <- |05  36| -> CHR A12 (r)
 (rn) CPU A12 -> |06  35| -> CHR A14 (r)
  (r) PRG A13 <- |07  34| <- PPU A12 (n)
  (r) PRG A16 <- |08  33| -> CHR A13 (r)
  (r) PRG /CE <- |09  32| -> CHR A16 (r)
 (rn) CPU  D4 -> |10  31| <- PPU  A8 (rn)
 (rn) CPU  D3 -> |11  30| <- PPU  A5 (rn)
 (rn) CPU  D0 -> |12  29| <- PPU  A9 (rn)
 (rn) CPU  D1 -> |13  28| <- PPU  A4 (rn)
 (rn) CPU  D2 -> |14  27| <- PPU A11 (rn)
  (n) CPU R/W -> |15  26| <- PPU  A3 (rn)
  (n) /ROMSEL -> |16  25| <- PPU  A7 (rn)
 (rn) PPU /RD -> |17  24| <- PPU  A2 (rn)
 (rn) PPU  A0 -> |18  23| <- PPU A10 (rn)
 (rn) PPU  A6 -> |19  22| <- PPU  A1 (rn)
          GND  - |20  21| <- PPU A13 (rn)
                 `------'

(r) - this pin connects to the ROM chips
(n) - this pin connects to the NES connector
Retrieved from "https://www.nesdev.org/w/index.php?title=MMC2_pinout&oldid=6445"