MMC1: Difference between revisions
(→Registers: rule out misleading "the fifth write has bit 7 set" interpretation of my last edit) |
(→Registers: Clarify ring-counter behavior) |
||
| Line 30: | Line 30: | ||
When the CPU writes to the serial port on consecutive cycles, the MMC1 ignores all writes but the first. | When the CPU writes to the serial port on consecutive cycles, the MMC1 ignores all writes but the first. | ||
This happens | This happens when the 6502 executes read-modify-write (RMW) instructions, such as DEC and ROR, by writing back the old value and then writing the new value on the next cycle. | ||
At least | At least ''Bill & Ted's Excellent Adventure'' resets the MMC1 by doing INC on a ROM location containing $FF; the MMC1 sees the $FF written back and ignores the $00 written on the next cycle. | ||
The hardware reason for this is believed to be that resetting and shifting happen on a falling edge of R/W, and RMW instructions hold R/W low for both writes. | The hardware reason for this is believed to be that resetting and shifting happen on a falling edge of R/W, and RMW instructions hold R/W low for both writes. | ||
| Line 40: | Line 40: | ||
; | ; | ||
; A MMC1_SR MMC1_PB | ; A MMC1_SR MMC1_PB | ||
setPRGBank: ; 000edcba 10000 | setPRGBank: ; 000edcba 10000 Start with an empty shift register (SR). The 1 is used | ||
sta $E000 ; 000edcba -> a1000 | sta $E000 ; 000edcba -> a1000 to detect when the SR has become full. | ||
lsr a ; >0000edcb a1000 | lsr a ; >0000edcb a1000 | ||
sta $E000 ; 0000edcb -> ba100 | sta $E000 ; 0000edcb -> ba100 | ||
| Line 47: | Line 47: | ||
sta $E000 ; 00000edc -> cba10 | sta $E000 ; 00000edc -> cba10 | ||
lsr a ; >000000ed cba10 | lsr a ; >000000ed cba10 | ||
sta $E000 ; 000000ed -> dcba1 | sta $E000 ; 000000ed -> dcba1 Once a 1 is shifted into the last position, the SR is full. | ||
lsr a ; >0000000e dcba1 | lsr a ; >0000000e dcba1 | ||
sta $E000 ; 0000000e dcba1 -> edcba A write with the SR full copies D0 and the SR to | sta $E000 ; 0000000e dcba1 -> edcba A write with the SR full copies D0 and the SR to a bank register | ||
; 10000 and then clears the SR | ; 10000 ($E000-$FFFF means PRG bank number) and then clears the SR. | ||
rts | rts | ||
</pre> | </pre> | ||
Revision as of 14:55, 17 June 2013
The Nintendo MMC1 is a mapper ASIC used in Nintendo's SxROM and NES-EVENT Game Pak boards. Most common SxROM boards are assigned to iNES Mapper 001. This chip first appeared in the April of 1987.
Overview
- PRG ROM size: Up to 256 KB depending on board
- PRG ROM bank size: 16 KB or 32 KB
- PRG RAM: Up to 8 KB
- CHR capacity: Up to 128 KB ROM or 8 KB RAM
- CHR bank size: 8 KB or 4 KB
- Nametable mirroring: Controlled by mapper
- Subject to bus conflicts: No
Banks
- CPU $6000-$7FFF: 8 KB PRG RAM bank, fixed
- CPU $8000-$BFFF: 16 KB PRG ROM bank, either switchable or fixed to the first bank
- CPU $C000-$FFFF: 16 KB PRG ROM bank, either fixed to the last bank or switchable
- PPU $0000-$0FFF: 4 KB switchable CHR bank
- PPU $1000-$1FFF: 4 KB switchable CHR bank
Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG ROM banks or to set up 32 KB PRG bankswitching (like BNROM), but most games use the default setup, which is similar to that of UxROM.
Registers
Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce pin count. CPU $8000-$FFFF is connected to a common shift register. Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state. To change a register's value, the CPU writes five times with bit 7 clear and a bit of the desired value in bit 0. On the first four writes, the MMC1 shifts bit 0 into a shift register. On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register. Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper registers are incompletely decoded like the PPU registers. After the fifth write, the shift register is cleared automatically, so a write to the shift register with bit 7 on to reset it is not needed.
When the CPU writes to the serial port on consecutive cycles, the MMC1 ignores all writes but the first. This happens when the 6502 executes read-modify-write (RMW) instructions, such as DEC and ROR, by writing back the old value and then writing the new value on the next cycle. At least Bill & Ted's Excellent Adventure resets the MMC1 by doing INC on a ROM location containing $FF; the MMC1 sees the $FF written back and ignores the $00 written on the next cycle. The hardware reason for this is believed to be that resetting and shifting happen on a falling edge of R/W, and RMW instructions hold R/W low for both writes.
To switch a bank, a program will execute code similar to the following:
;
; Sets the switchable PRG ROM bank to the value of A.
;
; A MMC1_SR MMC1_PB
setPRGBank: ; 000edcba 10000 Start with an empty shift register (SR). The 1 is used
sta $E000 ; 000edcba -> a1000 to detect when the SR has become full.
lsr a ; >0000edcb a1000
sta $E000 ; 0000edcb -> ba100
lsr a ; >00000edc ba100
sta $E000 ; 00000edc -> cba10
lsr a ; >000000ed cba10
sta $E000 ; 000000ed -> dcba1 Once a 1 is shifted into the last position, the SR is full.
lsr a ; >0000000e dcba1
sta $E000 ; 0000000e dcba1 -> edcba A write with the SR full copies D0 and the SR to a bank register
; 10000 ($E000-$FFFF means PRG bank number) and then clears the SR.
rts
But because only the fifth write sets the destination register, the following equivalent (if obfuscated) subroutine changes the PRG ROM bank in the same manner:
setPRGBank: sta $8765 lsr a sta $FACE lsr a sta $BA11 lsr a sta $AD2E lsr a sta $EAD5 rts
Load register ($8000-$FFFF)
7 bit 0
---- ----
Rxxx xxxD
| |
| +- Data bit to be shifted into shift register, LSB first
+--------- 1: Reset shift register and write Control with (Control OR $0C),
locking PRG ROM at $C000-$FFFF to the last bank.
Control (internal, $8000-$9FFF)
4bit0 ----- CPPMM ||||| |||++- Mirroring (0: one-screen, lower bank; 1: one-screen, upper bank; ||| 2: vertical; 3: horizontal) |++--- PRG ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number; | 2: fix first bank at $8000 and switch 16 KB bank at $C000; | 3: fix last bank at $C000 and switch 16 KB bank at $8000) +----- CHR ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)
CHR bank 0 (internal, $A000-$BFFF)
4bit0 ----- CCCCC ||||| +++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)
MMC1 can do CHR banking in 4KB chunks. Known carts with CHR RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.
CHR bank 1 (internal, $C000-$DFFF)
4bit0 ----- CCCCC ||||| +++++- Select 4 KB CHR bank at PPU $1000 (ignored in 8 KB mode)
PRG bank (internal, $E000-$FFFF)
4bit0 ----- RPPPP ||||| |++++- Select 16 KB PRG ROM bank (low bit ignored in 32 KB mode) +----- PRG RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)
Hardware
At least 6 different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B3, and MMC1C. The known differences are as follows:
- MMC1A: PRG RAM is always enabled
- MMC1B: PRG RAM is enabled by default.
- MMC1C: PRG RAM is disabled by default.
The MMC1 most commonly exists in a 24-pin shrink-DIP package.
Boards using an MMC1 may contain a battery connected to the PRG RAM's power line to preserve the data. Boards doing so will allow extra circuitery to be used, with 2 diodes and 2 resistors. A diode is needed from both voltage sources : The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery so that no current is drained from the battery when 5V is present. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger coupling capacity to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capcity, and saves are lost much more easily on those boards.
Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88)
Variants
Because the higher CHR lines aren't used when the MMC1 mapper is used with a 8KB CHR RAM, those lines are sometimes put to other uses depending on the board :
SNROM
CHR bank 0 (internal, $A000-$BFFF)
4bit0 ----- ExxxC | | | +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode) +----- PRG RAM disable (0: enable, 1: open bus)
CHR bank 1 (internal, $C000-$DFFF)
4bit0 ----- ExxxC | | | +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode) +----- PRG RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)
Both the E bit and the R bit (in standard MMC1 registers) should be clear in order for the PRG RAM to be writable or readable. This bit is more "reliable" on authentic hardware as it is implemented even in older boards with older MMC1's, while the R bit was only introduced later.
But because the E bit wasn't absolutely confirmed by the homebrew community until October 2010,[1] emulators tend not to implement it.
SOROM, SUROM and SXROM
CHR bank 0 (internal, $A000-$BFFF)
4bit0 ----- PSSxC ||| | ||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode) |++--- Select 8 KB PRG RAM bank +----- Select 256 KB PRG ROM bank
CHR bank 1 (internal, $C000-$DFFF)
4bit0 ----- PSSxC ||| | ||| +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode) |++--- Select 8 KB PRG RAM bank (ignored in 8 KB mode) +----- Select 256 KB PRG ROM bank (ignored in 8 KB mode)
The SOROM board only implement the upper S bit, while the SUROM board only implements the P bit.
The 256 KB PRG bank selection applies to all the PRG area, including the supposedly "fixed" bank.
In 4KB CHR bank mode, the P, S and E bits in both CHR bank registers must be set to the same values, or the PRG ROM and/or RAM will be bankswitched/enabled as the PPU renders, in a similar fashion as MMC3's scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.
References
- "Nintendo MMC1 info for 8-bit NES carts" by Matthew J. Richey
- MMC1 doc by Kevin Horton
- US Patent 4,949,298
