INES Mapper 243: Difference between revisions

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(→‎Register Data ($4101, read/write): call out that all registers can be fully read and written. fix typo in R4)
 
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[[Category:iNES Mappers|243]][[Category:Mappers using $4020-$5FFF|243]]
{{DEFAULTSORT:243}}[[Category:iNES Mappers]][[Category:Mappers using $4020-$5FFF]]
[[iNES Mapper 243]] describes Sachen's [[Sachen 74LS374N pinout|“74LS374N” mapper IC]], which in no way resembles its namesake.
'''iNES Mapper 243''' denotes the Sachen '''SA-020A''' circuit board. Using an eight-register ASIC with a fake "[[Sachen 74LS374N pinout|74LS374N]]" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, ''美女拳 - Honey Peach'' (SA-006).


Unfortunately, it seems that there are several different ways this board was wired. Submappers may need to be allocated.
=Banks=
* CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
* PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
* Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen


The IC, as described by Санчез, and as images in GoodNES, does not have any games with more than 64KiB PRG, so it's unclear why Nestopia or Санчез specify three bits for PRG banking.
=Registers=
 
==Register Index ($4100, write)==
  Example Games:
  Mask: $C101
  --------------------------
  Honey
  Poker III 5-in-1
 
  Registers:
  ---------------------------
  Mask: $E101
 
    $4100:  [.... .AAA]  Address for use with $4101
 
  Variant one (Nestopia calls "374b" and refiles to [[iNES Mapper 150]], but what Санчез specified) :
    $4101:  Data port
      R:2 -> [.... ...B] High bit of CHR reg AND ALSO sets PRG reg to B.
      R:4 -> [.... ...C]  Middle bit of CHR reg
      R:5 -> [.... .PPP]  PRG reg  (32k @ $8000)
      R:6 -> [.... ..DE]  Low bits of CHR reg
      R:7 -> [.... .MM.]  Mirroring
          %00 = Horz
          %01 = Vert
          %10 = L-shaped; see below
          %11 = 1ScA
   
   
    Nestopia asserts that both addresses are readable and return the inverted value of AAA, possibly XORed with some some unique ID.
D~7654 3210
 
   ---------
   Variant two (Nestopia calls "374a" and leaves as mapper 243, what Nocash specified) :
  .... .RRR
    $4101:  Data port
        +++- Select register number (Rx)
      R:0 -> [.... ....]  Writes reset CHR bank to 3 and PRG bank to 0
      R:2 -> [.... ...B]  High bit of CHR reg
      R:4 -> [.... ...E]  Low bit of CHR reg
      R:5 -> [.... ...P]  PRG reg  (32k @ $8000)
      R:6 -> [.... ..CD]  Middle bits of CHR reg
      R:7 -> [.... ...M]  Mirroring
            0 = Horz
            1 = Vert
 
  Mirroring:
  --------------------------- 
  Mirroring mode %10 is not quite 1ScB:
    [  NTA  ][  NTB  ]
    [  NTB  ][  NTB  ]
 
  CHR Setup:
  --------------------------- 
  8k CHR page @ $0000 is selected according to some permutation of the BCDE bits.


Of all the images marked as mapper 243 in GoodNES 3.1.4, Nestopia's database leaves ONLY ''Poker III (Sachen) [!]'' and ''Poker III (Sachen) [a1].nes'' as variant 374a, and refiles the rest as variant 374b.
==Register Data ($4101, read/write)==
 
Mask: $C101
There are two different dumps of "Poker III" in GoodNES, both marked with [!]. This has caused some confusion. There is no difference in the PRG of these two images! The only difference seems to be the different interpretation of CHR order. Given that Санчез described the pinout, and so presumably actually figured out which pin connected to which pin on the ROMs, it seems not unlikely that all of GoodNES (and No-intro)'s "authoritative" dumps may be wrong.
D~7654 3210
  ---------
  .... .RRR
        +++- Register data
D~7654 3210
  ---------
  .... ...A  R2: CHR A13
  .... ...B  R4: CHR A14
  .... ..PP  R5: PRG A16..A15
  .... ..DC  R6: CHR A16..A15
  ...  .MM.  R7: Nametable mirroring
              0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L)
              1: Horizontal
              2: Vertical
              3: Single-screen, page 1
Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to.


This still doesn't address the difference in mirroring behavior. Nocash says that no game ever wrote anything other than $05 to the register anyway.
=Errata=
The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.


Reference: Санчез ( http://cah4e3.shedevr.org.ru/%5Blst%5D-sachen-mappers.txt ), [https://github.com/rdanbrook/nestopia/blob/master/source/core/board/NstBoardSachen74x374.cpp Nestopia's source], [http://nocash.emubase.de/everynes.htm#mapper243sachenpokerprg32kvrom8k Nocash]
=See also=
* [https://www.flickr.com/photos/153392699@N08/sets/72157682682439086 Box, Cart, and PCB picture of ''Honey Peach'']

Latest revision as of 19:21, 14 December 2019

iNES Mapper 243 denotes the Sachen SA-020A circuit board. Using an eight-register ASIC with a fake "74LS374N" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, 美女拳 - Honey Peach (SA-006).

Banks

  • CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
  • PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
  • Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen

Registers

Register Index ($4100, write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Select register number (Rx)

Register Data ($4101, read/write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Register data

D~7654 3210
  ---------
  .... ...A  R2: CHR A13
  .... ...B  R4: CHR A14
  .... ..PP  R5: PRG A16..A15
  .... ..DC  R6: CHR A16..A15
  ...  .MM.  R7: Nametable mirroring
              0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L)
              1: Horizontal
              2: Vertical
              3: Single-screen, page 1

Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to.

Errata

The SA-150 PCB, denoted by INES Mapper 150, connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.

See also

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