INES Mapper 159: Difference between revisions

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(only latch on this mapper)
(→‎Registers: what's the distinction between the X24C01 and 24C01? elucidate.)
 
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[[Category:iNES Mappers|159]][[Category:Mappers with cycle IRQs|159]]
[[Category:iNES Mappers|159]][[Category:Mappers with cycle IRQs|159]]
iNES Mapper 159 is used for Bandai '''FCG''' boards with an LZ93D50 ASIC and a 128-byte serial EEPROM (24C01). The 128 bytes must be denoted as PRG-NVRAM in the [[NES 2.0]] header using byte value $10.
iNES Mapper 159 is used for [[Bandai FCG]] boards with an [[Bandai LZ93D50 pinout|LZ93D50 ASIC]] and a 128-byte serial EEPROM (X24C01). The 128 bytes must be denoted as PRG-NVRAM in the [[NES 2.0]] header using byte value $10.
=Game List=
=Game List=
* ''Dragon Ball Z: Kyoushuu! Saiya-jin''
* ''Dragon Ball Z: Kyoushuu! Saiya-jin''
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=Registers=
=Registers=
==Read Serial EEPROM ($6000-$7FFF read)==
All registers function the same way as [[INES Mapper 016]], submapper 5, except that the serial EEPROM is not a 24C02 but Xicor's X24C01. This EEPROM has operational differences compared to both the larger 24C02 and other vendors' 24C01. Bandai's developers consistently thought the X24C01 was a little-endian device, and their code clocks in address and data bytes assuming this. However, it's actually a big-endian device, and a multi-byte read or write from EEPROM will increment the address accordingly.
Mask: $E000
7  bit  0
---- ----
xxxE xxxx
|||| ||||
+++|-++++- Open bus
    +------ Data out from I²C EEPROM
==CHR-ROM Bank Select ($8000-$8007 write)==
Mask: $800F
7  bit  0
---- ----
CCCC CCCC
|||| ||||
++++-++++-- 1 KiB CHR-ROM bank number
* $xxx0: Select 1 KiB CHR-ROM bank at PPU $0000-$03FF
* $xxx1: Select 1 KiB CHR-ROM bank at PPU $0400-$07FF
* $xxx2: Select 1 KiB CHR-ROM bank at PPU $0800-$0BFF
* $xxx3: Select 1 KiB CHR-ROM bank at PPU $0C00-$0FFF
* $xxx4: Select 1 KiB CHR-ROM bank at PPU $1000-$13FF
* $xxx5: Select 1 KiB CHR-ROM bank at PPU $1400-$17FF
* $xxx6: Select 1 KiB CHR-ROM bank at PPU $1800-$1BFF
* $xxx7: Select 1 KiB CHR-ROM bank at PPU $1C00-$1FFF
==PRG-ROM Bank Select ($8008 write)==
Mask: $800F
7  bit  0
---- ----
.... PPPP
      ||||
      ++++-- Select 16 KiB PRG-ROM bank at CPU $8000-$BFFF 
==Nametable Mirroring Type Select ($8009 write)==
Mask: $800F
7  bit  0
---- ----
.... ..MM
        ||
        ++-- Select nametable mirroring type
      0: Vertical
      1: Horizontal
      2: One-screen, page 0
      3: One-screen, page 1
==IRQ Control ($800A write)==
Mask: $800F
7  bit  0
---- ----
.... ...C
        |
        +-- IRQ counter control
    0: Counting disabled
    1: Counting enabled
* Writing to this register acknowledges a pending IRQ, and copies the latch to the actual counter.
* If a write to this register enables counting while the counter is holding a value of zero, an IRQ is generated immediately.
==IRQ Latch ($800B-$800C write)==
Mask: $800F
    $C        $B
7  bit  0  7  bit  0
---- ----  ---- ----
CCCC CCCC  CCCC CCCC
|||| ||||  |||| ||||
++++-++++--++++-++++-- Counter value (little-endian)
* If counting is enabled, the counter decreases on every M2 cycle. When it holds a value of zero, an IRQ is generated.
* These registers modify a latch that will only be copied to the actual counter when register $xxxA is written to.
==EEPROM Control ($800D write)==
Mask: $800F
7  bit  0
---- ----
RDC. ....
|||
||+-------- I²C SCL
|+--------- I²C SDA
+---------- Direction bit (1=Enable Read)
 
* This register only has an effect if a 24C01 EEPROM is present.
* Please refer to generic I²C tutorials and the 24C01 datasheet on how to operate or emulate this register correctly.

Latest revision as of 00:11, 10 May 2020

iNES Mapper 159 is used for Bandai FCG boards with an LZ93D50 ASIC and a 128-byte serial EEPROM (X24C01). The 128 bytes must be denoted as PRG-NVRAM in the NES 2.0 header using byte value $10.

Game List

  • Dragon Ball Z: Kyoushuu! Saiya-jin
  • Magical Taruruuto-kun: Fantastic World!!
  • Magical Taruruuto-kun 2: Mahou Daibouken
  • SD Gundam Gaiden - Knight Gundam Monogatari

Banks

  • CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
  • CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
  • PPU $0000-$03FF: 1 KiB switchable CHR ROM bank
  • PPU $0400-$07FF: 1 KiB switchable CHR ROM bank
  • PPU $0800-$0BFF: 1 KiB switchable CHR ROM bank
  • PPU $0C00-$0FFF: 1 KiB switchable CHR ROM bank
  • PPU $1000-$13FF: 1 KiB switchable CHR ROM bank
  • PPU $1400-$17FF: 1 KiB switchable CHR ROM bank
  • PPU $1800-$1BFF: 1 KiB switchable CHR ROM bank
  • PPU $1C00-$1FFF: 1 KiB switchable CHR ROM bank

Registers

All registers function the same way as INES Mapper 016, submapper 5, except that the serial EEPROM is not a 24C02 but Xicor's X24C01. This EEPROM has operational differences compared to both the larger 24C02 and other vendors' 24C01. Bandai's developers consistently thought the X24C01 was a little-endian device, and their code clocks in address and data bytes assuming this. However, it's actually a big-endian device, and a multi-byte read or write from EEPROM will increment the address accordingly.

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