INES Mapper 095: Difference between revisions
m (agreed; cribbed the TxSROM description and removed disch's description. Contemplated fixing it instead of removing it but decided it was too redundant.) |
(wasnt happy with the last m095, i thought for 20 minutes that it was functionally changed before I understood it. Tried explaining it differently.) |
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| Line 11: | Line 11: | ||
7 bit 0 | 7 bit 0 | ||
---- ---- | ---- ---- | ||
.. | ..ND DDDD | ||
|| |||| | || |||| | ||
|+-++++- New bank value, based on last value written to Bank select register | |+-++++- New bank value, based on last value written to Bank select register | ||
| | | All registers as standard [[iNES Mapper 206|Namco 108]] | ||
| | | | ||
+------- | +------- Nametable select, based on last value written to Bank select register | ||
0: Select Nametable A | |||
0: Select Nametable at PPU $2000-$27FF (top left | 1: Select Nametable B | ||
The nametable at PPU $2000-$27FF (top left/right) are controlled with register 0 | |||
The nametable at PPU $2800-$2FFF (bottom left/right) are controlled with register 1 | |||
Revision as of 20:34, 15 June 2012
Mapper 95 represents NAMCOT-3425, a board that is to the ordinary Namco 108 family boards (mapper 206) as TKSROM and TLSROM (mapper 118) is to ordinary MMC3 boards (mapper 4). Instead of having hardwired mirroring like mapper 206, it has CHR A15 directly controlling CIRAM A10, just as CHR A17 controls CIRAM A10 on TxSROM. Only horizontal mirroring and 1-screen mirroring are possible because the Namco 108 lacks the C bit of MMC3. It is used for Dragon Buster (J), which has 32 KiB of CHR ROM. The mapper could be extended to 64 KiB through careful arrangement of CHR ROM to put game background tiles in one half (which would always use one nametable) and status bar and menu tiles in the other half (which would always use the other nametable).
Disch's older notes described an extended and mistaken version of this mapper with a full MMC3, so some emulators may be doing it that way. That extended version is identical to mapper 118, except CHR A15 (bank bit 5) controls CIRAM A10 instead of CHR A17 (bank bit 7).
Bank data ($8001-$9FFF, odd)
7 bit 0 ---- ---- ..ND DDDD || |||| |+-++++- New bank value, based on last value written to Bank select register | All registers as standard Namco 108 | +------- Nametable select, based on last value written to Bank select register 0: Select Nametable A 1: Select Nametable B The nametable at PPU $2000-$27FF (top left/right) are controlled with register 0 The nametable at PPU $2800-$2FFF (bottom left/right) are controlled with register 1
