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| Here are Disch's original notes:
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| ========================
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| = Mapper 064 =
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| ========================
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|
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|
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| aka
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| --------------------------
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| Tengen [[RAMBO-1]]
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|
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|
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|
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| Example Games:
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| --------------------------
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| Klax
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| Skull and Crossbones
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| Shinobi
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|
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|
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| Notes:
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| --------------------------
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| This mapper is very similar to [[MMC3]]. It uses a similar swapping system, but adds a little functionality.
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|
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| IRQs are set up similar as well... but have some major differences.
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|
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| This is one of those mappers that is a big pain to implement in an emu -- especially since so few games use
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| it. And the games that use it really blow hard.
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|
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|
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| Registers:
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| --------------------------
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|
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| Range,Mask: $8000-FFFF, $E001
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|
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| $8000: [CPK. AAAA]
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| C = CHR mode select
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| P = PRG mode select
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| K = full 1k CHR mode select (see CHR setup)
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| A = Address for use with $8001
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|
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| $8001: [DDDD DDDD] Data port
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| R:0 -> CHR reg 0
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| R:1 -> CHR reg 1
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| R:2 -> CHR reg 2
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| R:3 -> CHR reg 3
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| R:4 -> CHR reg 4
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| R:5 -> CHR reg 5
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| R:6 -> PRG reg 0
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| R:7 -> PRG reg 1
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| R:8 -> CHR reg 6
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| R:9 -> CHR reg 7
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| R:A - R:E not used
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| R:F -> PRG reg 2
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|
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| $A000: [.... ...M] Mirroring
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| 0 = Vert
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| 1 = Horz
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| $C000: [IIII IIII] IRQ Reload value
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| $C001: [.... ...M] IRQ Mode select and reset
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| 0 = Scanline (A12) mode
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| 1 = Cycle mode
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|
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| $E000: [.... ....] IRQ Acknowledge/Disable
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| $E001: [.... ....] IRQ Enable
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|
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|
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| PRG Setup:
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| ---------------------------
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|
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| PRG mode is selected via $8000.6
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|
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| $8000 $A000 $C000 $E000
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| +-------+-------+-------+-------+
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| PRG Mode 0: | R:6 | R:7 | R:F | { -1} |
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| +-------+-------+-------+-------+
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| PRG Mode 1: | R:F | R:6 | R:7 | { -1} |
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| +-------+-------+-------+-------+
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|
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|
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| CHR Setup:
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| ---------------------------
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|
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| $8000 has 2 bits to configure CHR modes. Therefore there are effectively 4 CHR modes.
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|
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| $8000: [CPK. AAAA] <--- C and K bits relevant to CHR
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|
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|
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| $0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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| +---------------+---------------+-------+-------+-------+-------+
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| C=0, K=0 | <R:0> | <R:1> | R:2 | R:3 | R:4 | R:5 |
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| +---------------+---------------+-------+-------+-------+-------+
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| C=0, K=1 | R:0 | R:8 | R:1 | R:9 | R:2 | R:3 | R:4 | R:5 |
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| +-------+-------+-------+-------+---------------+---------------+
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| C=1, K=0 | R:2 | R:3 | R:4 | R:5 | <R:0> | <R:1> |
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| +-------+-------+-------+-------+---------------+---------------+
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| C=1, K=1 | R:2 | R:3 | R:4 | R:5 | R:0 | R:8 | R:1 | R:9 |
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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|
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|
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| IRQs:
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| ---------------------------
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|
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| There are two separate IRQ modes. One uses A12 to count scanlines in a manner just like MMC3 does (see
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| mapper 004 for details on how scanlines are counted and the restrictions involved). The other mode uses CPU
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| cycles with a 4-step prescaler (so the IRQ counter gets clocked every 4 CPU cycles).
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|
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| Regardless of the mode used to clock the counter... every time the counter is clocked, the following actions
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| occur:
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|
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| - If Reset reg ($C001) was written to after previous clock...
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| a) reload IRQ counter with IRQ Reload value **PLUS ONE**
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|
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| - Otherwise... If IRQ Counter is 0...
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| a) reload IRQ counter with IRQ Reload value
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|
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| - Otherwise...
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| a) Decrement IRQ counter by 1
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| b) If IRQ counter is now 0 and IRQs are enabled, trigger IRQ
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|
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|
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| Just like with MMC3, the counter is clocked and updated even when IRQs are disabled -- however IRQs will only
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| be triggered when enabled.
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|
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| Note about the plus one: I'm not sure if 1 is really added or if there's simply an additional 1 clock delay
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| before the IRQ counter is updated. From a software standpoint, it doesn't really matter -- adding the
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| additional 1 works without any side-effects.
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|
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|
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| Registers involved with IRQs:
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| ---------------------------
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|
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| $C000: [IIII IIII] - IRQ Reload value
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|
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| $C001: [.... ...M] - IRQ Reset reg, mode select
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| 0 = Scanline mode (A12)
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| 1 = CPU Cycle mode (with prescaler)
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|
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| Any write to this register will make it so that the IRQ counter will reload with the reload value +1 on
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| its next clock. Whether or not writing to this register clears the IRQ counter like it does with MMC3 isn't
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| known... and doesn't matter, since it's reloaded later anyway.
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|
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| Also, any write to this register will reset the CPU cycle prescaler (so that it will be 4 CPU cycles
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| until the next clock).
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|
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| $E000: [.... ....] - IRQ Acknowledge/Disable
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| Any write to this register will acknowledge the pending IRQ, and disable IRQs
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|
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| $E001: [.... ....] - IRQ Enable
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| Any write to this register will enable IRQs
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|
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| A note about IRQs:
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| ------------------
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|
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| Scanline IRQs seem to trip a little later than they do on the MMC3. It looks like about a 5 dot delay
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| from the normal MMC3 IRQ time (265 instead of 260). Failure to put in this delay results in shaking and
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| other graphical quirks in some games... notably Klax. This delay also seems to exist for CPU cycle driven
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| IRQs (Skull & Crossbones will suffer without it). Perhaps the RAMBO-1's IRQ generating hardware is a little
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| slower than usual?
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|
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| Apart from that timing difference, A12 clocks RAMBO-1's IRQ counter just exactly like it does MMC3, so all
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| the notes about A12, $2006/7, etc from the mapper 004 documentation apply to this mapper as well.
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|
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| [[Category:iNES Mappers|064]][[Category:MMC3-like mappers|064]][[Category:in NesCartDB|064]] | | [[Category:iNES Mappers|064]][[Category:MMC3-like mappers|064]][[Category:in NesCartDB|064]] |
| | [[iNES Mapper 064]] represents almost all but [[iNES Mapper 158|one]] of Tengen's boards that used the [[RAMBO-1]] mapper. |
