INES Mapper 052: Difference between revisions
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$6000 set to 0 on reset and powerup. | $6000 set to 0 on reset and powerup. | ||
The multicart register here can be implemented using two ICs: a 74273 (8 bit latch with asynchronous clear) and a 74153 (used as two independent one-of-two multiplexers). The 74273's /CLEAR input should be connected to something like | |||
CPU M2 or CPU A0 --|>|--+-+-- /CLEAR | |||
| | | |||
R C | |||
| | | |||
gnd gnd | |||
* Diode: 1N914 or any other small signal diode | |||
* Resistor: approximately 10kΩ | |||
* Capacitor: approximately 1nF |
Revision as of 22:29, 9 May 2014
These notes were updated on 2013-11-19 in response to this thread on the forum.
iNES Mapper 052, like several other multicart mappers, supplements the MMC3's RAM with a single register for switching between unmodified MMC3-compatible games.
Registers: --------------------------- $6000-7FFF: [WMCC SBPP] Multicart reg P = PRG Block (bits 1,0) = PRG A18 and A17 B = CHR+PRG Block Select bit (PRG and CHR bit 2) = CHR and PRG A19 S = PRG Block size (0=256k 1=128k) = 0=PRG A17 comes from MMC3 1=A17 comes from this register C = CHR Block (bits 1,0) = CHR A18 and A17 M = CHR Block size (0=256k 1=128k) = 0=CHR A17 comes from MMC3 1=A17 comes from this register W = 1=Disable multicart register and enable RAM 0=allow further writes to multicart register $8000-FFFF: Same as MMC3 for selected block This register can only be written to if PRG-RAM is enabled and writable (see $A001). PRG Setup: --------------------------- 'S' PRG-AND PRG-OR ------------------------ 0 $1F %BP0 0000 1 $0F %BPP 0000 'B' and 'P' bits make a 3-bit value used as PRG-OR (left shift 4). When 'S' is clear, the low bit of that value is forced to 0. PRG swapping behaves just like a normal MMC3 within this selected block CHR Setup: --------------------------- 'M' CHR-AND CHR-OR ------------------------ 0 $FF %BC 0000 0000 1 $7F %BC C000 0000 'B' and 'C' bits make a 3-bit value used as CHR-OR (left shift 7). When 'M' is clear, the low bit of that value is forced to 0. CHR swapping behaves just like a normal MMC3 within this selected block Powerup and Reset: --------------------------- $6000 set to 0 on reset and powerup.
The multicart register here can be implemented using two ICs: a 74273 (8 bit latch with asynchronous clear) and a 74153 (used as two independent one-of-two multiplexers). The 74273's /CLEAR input should be connected to something like
CPU M2 or CPU A0 --|>|--+-+-- /CLEAR | | R C | | gnd gnd
- Diode: 1N914 or any other small signal diode
- Resistor: approximately 10kΩ
- Capacitor: approximately 1nF