INES Mapper 036: Difference between revisions
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(rephrase lede because Gluk didn't publish Strike Wolf) |
(Use uniform terminology to attempt to clarify) |
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| Line 14: | Line 14: | ||
read $4100-4103: [xxRR xxxx] | read $4100-4103: [xxRR xxxx] | ||
|||| |||| | |||| |||| | ||
||++------ | ||++------ Copy internal register 'RR' to data bus. | ||
++---++++- open bus | ++---++++- open bus | ||
write $4100: when M=0, copy PP to RR. When M=1, RR=RR+1 | write $4100: when M=0, copy internal register 'PP' to internal register 'RR'. When M=1, RR=RR+1 | ||
write $4101: no visible effect | write $4101: no visible effect | ||
write $4102: [..PP ....] - | write $4102: [..PP ....] - Copy data bus to internal register 'PP'. Value is not yet exposed anywhere. | ||
write $4103: [...M ....] - PRG banking mode (0: copy, 1: increment) | write $4103: [...M ....] - PRG banking mode (0: copy, 1: increment) | ||
write $8000-$FFFF: copy RR to PRG banking pins | write $8000-$FFFF: copy internal register 'RR' to PRG banking pins | ||
This PRG behavior is confusing but seems to be complete. | This PRG behavior is confusing but seems to be complete. | ||
| Line 26: | Line 26: | ||
The ''05-00002-010'' ASIC is connected as: | The ''05-00002-010'' ASIC is connected as: | ||
.--\/--. | .--\/--. | ||
¹NC <- |01 24| -> | ¹NC <- |01 24| -> NC¹ | ||
(r) PRG A16 <- |02 23| -> | (r) PRG A16 <- |02 23| -> NC² | ||
(r) PRG A15 <- |03 22| -> | (r) PRG A15 <- |03 22| -> NC³ | ||
GND ?? |04 21| <- CPU A13 (rn) | GND ?? |04 21| <- CPU A13 (rn) | ||
5V ?? |05 20| <- CPU A14 (rn) | 5V ?? |05 20| <- CPU A14 (rn) | ||
²NC <> |06 19| ?? GND | |||
5V ?? |07 18| <- CPU R/W (n) | 5V ?? |07 18| <- CPU R/W (n) | ||
²NC <> |08 17| <- /ROMSEL (rn) | |||
²NC <> |09 16| <- M2 (n) | |||
¹NC <> |10 15| <- CPU A8 (rn) | ¹NC <> |10 15| <- CPU A8 (rn) | ||
(rn) CPU D5 <> |11 14| <- CPU A1 (rn) | (rn) CPU D5 <> |11 14| <- CPU A1 (rn) | ||
| Line 40: | Line 40: | ||
'------' | '------' | ||
¹: pins 1 and | ¹: pins 1, 10, and 24 could respectively function as PRG A17, CPU D6, and PRG A18 if they were connected. | ||
PRG A18 can only be toggled by using the increment behavior | |||
²: pins 6,8,9, and 23 could respectively function as CPU D0, D1, D2, and CHR A13 if they were connected; | |||
however writes to $4101 then cause extra obfuscatory behavior | |||
³: Defective, always high | |||
Three additional games published by Gluk use the same PCB, with no ASIC. They were also released in other regions on different hardware, and ''only'' Gluk's editions are compatible with the above-mentioned CHR banking. | Three additional games published by Gluk use the same PCB, with no ASIC. They were also released in other regions on different hardware, and ''only'' Gluk's editions are compatible with the above-mentioned CHR banking. | ||
Revision as of 20:04, 6 August 2017
iNES Mapper 036 is assigned to TXC's PCB 01-22000-400, featuring a 74138, a 74175, and usually a 24-pin ASIC labeled 05-00002-010. Two games are currently known to require this definition.
- Strike Wolf
- Policeman
Even though these games can evidently be emulated as a weird kind of GNROM, the hardware does something quite different:
The CHR banking is definitely implemented using the two 7400-series ICs:
Mask: $E200 write $4200: [.... CCCC] - Select 8 KiB CHR bank
The PRG banking is part of the ASIC:
Mask: $E103
read $4100-4103: [xxRR xxxx]
|||| ||||
||++------ Copy internal register 'RR' to data bus.
++---++++- open bus
write $4100: when M=0, copy internal register 'PP' to internal register 'RR'. When M=1, RR=RR+1
write $4101: no visible effect
write $4102: [..PP ....] - Copy data bus to internal register 'PP'. Value is not yet exposed anywhere.
write $4103: [...M ....] - PRG banking mode (0: copy, 1: increment)
write $8000-$FFFF: copy internal register 'RR' to PRG banking pins
This PRG behavior is confusing but seems to be complete.
The 05-00002-010 ASIC is connected as:
.--\/--.
¹NC <- |01 24| -> NC¹
(r) PRG A16 <- |02 23| -> NC²
(r) PRG A15 <- |03 22| -> NC³
GND ?? |04 21| <- CPU A13 (rn)
5V ?? |05 20| <- CPU A14 (rn)
²NC <> |06 19| ?? GND
5V ?? |07 18| <- CPU R/W (n)
²NC <> |08 17| <- /ROMSEL (rn)
²NC <> |09 16| <- M2 (n)
¹NC <> |10 15| <- CPU A8 (rn)
(rn) CPU D5 <> |11 14| <- CPU A1 (rn)
(rn) CPU D4 <> |12 13| <- CPU A0 (rn)
'------'
¹: pins 1, 10, and 24 could respectively function as PRG A17, CPU D6, and PRG A18 if they were connected.
PRG A18 can only be toggled by using the increment behavior
²: pins 6,8,9, and 23 could respectively function as CPU D0, D1, D2, and CHR A13 if they were connected;
however writes to $4101 then cause extra obfuscatory behavior
³: Defective, always high
Three additional games published by Gluk use the same PCB, with no ASIC. They were also released in other regions on different hardware, and only Gluk's editions are compatible with the above-mentioned CHR banking.
- F-15 City War
- Volley ball
- Puzzle
Compatibility code left in means that all editions of these three games are emulatable as NINA-06.
See also:
- http://forums.nesdev.org/viewtopic.php?p=167180#p167180 Thread about dumping Policeman starts here
