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| [[Category:iNES Mappers]] | | #REDIRECT [[VRC6]] |
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| [[iNES Mapper 024]] is used to represent one variant of the Konami [[VRC6]] mapper. | | {{DEFAULTSORT:024}}[[Category:iNES Mappers]][[Category:in NesCartDB]][[Category:Mappers with cycle IRQs]] |
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| Here are Disch's original notes:
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| ========================
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| = Mapper 024 =
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| = + 026 =
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| ========================
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|
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| aka
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| --------------------------
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| VRC6
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| Example Games:
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| --------------------------
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| Akumajou Densetsu (024)
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| Madara (026)
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| Esper Dream 2 (026)
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| Multiple numbers, just one mapper:
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| --------------------------
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| As is the VRC way... VRC6 comes in two varieties. Both variants operate exactly the same, only the reigster
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| addresses are different:
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|
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| variant lines registers Mapper Number
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| =================================================================
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| VRC6a: A0, A1 $x000, $x001, $x002, $x003 024
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| VRC6b: A1, A0 $x000, $x002, $x001, $x003 026
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| This doc will use the 'VRC6a' registers (0,1,2,3) in all following register descriptions. For 'VRC6b',
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| simply reverse $x001 and $x002.
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| Registers:
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| --------------------------
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| Some registers are mirrored across several addresses. For example, writing to $8003 has the same effect as
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| writing to $8000.
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| $8000-$8003: [PPPP PPPP] PRG Reg 0 (Select 16k @ $8000)
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| $9000-$9002: Sound, Pulse 1 (see sound section)
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| $A000-$A002: Sound, Pulse 2
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| $B000-$B002: Sound, Sawtooth
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| $B003: [.... MM..] Mirroring:
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| %00 = Vert
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| %01 = Horz
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| %10 = 1ScA
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| %11 = 1ScB
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| $C000-$C003: [PPPP PPPP] PRG Reg 1 (Select 8k @ $C000)
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| $D000-$E003: [CCCC CCCC] CHR regs (See CHR setup)
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| $F000-$F002: IRQ regs (See IRQ section)
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| PRG Setup:
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| --------------------------
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| $8000 $A000 $C000 $E000
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| +---------------+-------+-------+
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| | $8000 | $C000 | { -1} |
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| +---------------+-------+-------+
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| CHR Setup:
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| --------------------------
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| $0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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| | $D000 | $D001 | $D002 | $D003 | $E000 | $E001 | $E002 | $E003 |
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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| IRQs:
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| --------------------------
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| VRC6 use the "VRC IRQ" setup shared by several VRCs. It uses the following registers:
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| $F000: [IIII IIII] IRQ Reload
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| $F001: [.... .MEA] IRQ Control
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| $F002: [.... ....] IRQ Acknowledge
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| For info on how these IRQs work, see the "VRC IRQs" section in mapper 021
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|
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|
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| ==========================
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| Sound:
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| --------------------------
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| VRC6 has two additional pulse channels, and one sawtooth channel. Both operate very similarly to the NES's
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| native channels.
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| Pulse Channels:
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| ------------------------
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| $9000, $A000: [MDDD VVVV]
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| M = Mode (0=normal mode, 1=digitized mode)
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| D = Duty cycle (duty cycle is (D+1)/16)
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| V = Volume
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| $9001, $A001: [FFFF FFFF]
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| F = Low 8 bits of Frequency
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| $9002, $A002: [E... FFFF]
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| F = High 4 bits of Frequency
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| E = Channel Enable (0=disabled, 1=enabled)
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| Pulse 1 uses regs $900x
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| Pulse 2 uses regs $A00x
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| Just like the NES's own pulse channels, an internal counter is counted down each CPU cycle, and when it
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| wraps, it's reloaded with the 'F' frequency value, and the duty cycle unit takes another step. VRC6's pulses
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| can have a duty cycle anywhere between 1/16 and 8/16 depending on the given 'D' value.
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| Channel output is either 0 or 'V', depending on the current state of the duty cycle unit (or digitized
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| mode).
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| When 'M' is set (digitized mode), the duty cycle is ignored, and 'V' is always output. In this mode, the
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| channel essentially is no longer a Pulse wave, but rather $9000/$A000 acts like a 4-bit PCM streaming
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| register (similar to $4011).
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|
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| When 'E' is clear (channel disabled), output of the channel is forced to '0' (silencing the channel).
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| Generated tone in Hz can be calculated by the following:
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|
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| CPU_CLOCK
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| Hz = -------------
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| (F+1) * 16
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|
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| Sawtooth Channel:
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| ------------------------
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|
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| $B000: [..AA AAAA]
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| A = Accum Rate
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| $B001: [FFFF FFFF]
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| F = Low 8 bits of frequency
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| $B002: [E... FFFF]
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| F = High 4 bits of frequency
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| E = Channel Enable (0=disabled, 1=enabled)
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| The sawtooth uses an 8-bit accumulation register. Every time it is clocked, 'A' is added until the 7th
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| clock, at which point it is reset to 0. The high 5 bits of this accumulation reg are then used as the
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| channel output. Strangely, though, the accumulation register seems to only be clocked once for every *two*
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| times the frequency divider expires. This results in a tone that's an octave lower than you might expect.
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| It's difficult to put in words, so here's an example using $0B as a value for the accum rate ('A'):
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| Step Accum. Channel output
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| -------------------------------
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| 0 $00 $00
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| 1 $00 $00 odd steps do nothing
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| 2 $0B $01 even steps.. add value of 'A' to accum
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| 3 $0B $01
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| 4 $16 $02
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| 5 $16 $02
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| 6 $21 $04
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| 7 $21 $04
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| 8 $2C $05
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| 9 $2C $05
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| 10 $37 $06
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| 11 $37 $06
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| 12 $42 $08 6th and final time 'A' is added
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| 13 $42 $08
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| 0 $00 $00 7th time, accum is reset instead
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| ... and the process repeats
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| Channel output is the high 5 bits of the accumulation reg (right shift reg by 3). If the accum rate is too
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| high, the accum reg WILL wrap at 8 bits, causing ugly distortion. The highest accum rate you can use without
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| wrapping is $2A.
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| If 'E' is clear (channel disabled), channel output is forced to 0 (silencing the channel).
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| Generated tone in Hz can be calculated by the following:
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| CPU_CLOCK
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| Hz = -------------
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| (F+1) * 14
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