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| [[Category:iNES Mappers|021]][[Category:in NesCartDB|021]] | | #REDIRECT [[VRC2 and VRC4]] |
| | | {{DEFAULTSORT:021}}[[Category:iNES Mappers]][[Category:in NesCartDB]][[Category:NES 2.0 mappers with submappers]][[Category:Mappers with cycle IRQs]] |
| [[iNES Mapper 021]] is used to represent the VRC4a (PCB '''352398''') and VRC4c (PCB '''352889''') variants of the Konami [[VRC4]] mapper.
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| Here are Disch's original notes:
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| ========================
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| = Mapper 021 =
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| = + 023 =
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| = + 025 =
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| ========================
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|
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| aka
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| --------------------------
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| [[VRC4]]
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|
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|
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|
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| Example Games:
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| --------------------------
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| Wai Wai World 2 (021)
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| Ganbare Goemon Gaiden 2 (021)
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| Boku Dracula-kun (023)
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| Tiny Toon Adventures (J) (023)
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| Gradius 2 (J) (025)
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| Bio Miracle Bokutte Upa (025)
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|
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|
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|
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| Multiple numbers, just one mapper:
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| --------------------------
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| These three mapper numbers (021, 023, 025) collectively represent different wiring variations of the same mapper:
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| VRC4. Each variation operates exactly the same, only the registers used are different because they all use
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| different address lines. Some lines are even reversed from the norm.
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|
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| variant lines registers Mapper Number
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| =================================================================
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| VRC4a: A1, A2 $x000, $x002, $x004, $x006 021
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| VRC4b: A1, A0 $x000, $x002, $x001, $x003 025
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| VRC4c: A6, A7 $x000, $x040, $x080, $x0C0 021
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| VRC4d: A3, A2 $x000, $x008, $x004, $x00C 025
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| VRC4e: A2, A3 $x000, $x004, $x008, $x00C 023
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| VRC4f: A0, A1 $x000, $x001, $x002, $x003 023
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| VRC4f may not exist, see [[Talk:VRC4]]
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|
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| This doc will use the 'VRC4a' registers (0,2,4,6) in all following register descriptions. For other
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| variants, use the above chart to convert.
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|
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| Registers:
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| --------------------------
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| Some registers are mirrored across several addresses. For example, writing to $9004 has the same effect as
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| writing to $9006.
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|
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| $8000-$8006: [...P PPPP] PRG Reg 0
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| $9000,$9002: [.... ..MM] Mirroring:
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| %00 = Vert
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| %01 = Horz
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| %10 = 1ScA
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| %11 = 1ScB
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|
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| $9004,$9006: [.... ..M.] PRG Swap Mode Select
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| $A000-$A006: [...P PPPP] PRG Reg 1
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| $B000-$E006: [.... CCCC] CHR Regs (see CHR Setup)
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|
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| $F000+$F002: [.... IIII] IRQ Reload Value (see IRQ section)
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| $F004 [.... .MEA] IRQ Control (see IRQ section)
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| $F006 [.... ....] IRQ Acknowledge (see IRQ section)
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|
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|
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| PRG Setup:
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| --------------------------
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| There are two PRG modes, which can be seleted via $9004.
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|
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| $8000 $A000 $C000 $E000
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| +-------+-------+-------+-------+
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| PRG Mode 0: | $8000 | $A000 | { -2} | { -1} |
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| +-------+-------+-------+-------+
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| PRG Mode 1: | { -2} | $A000 | $8000 | { -1} |
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| +-------+-------+-------+-------+
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|
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|
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| CHR Setup:
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| --------------------------
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| The VRC4 only has 4 data pins for CHR Regs. To compensate, two CHR regs are combined to form a single page
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| number. One reg contains the high 4 bits and the other reg contains the low 4 bits (allowing for 8-bit page
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| numbers)
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|
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| Example: $B000+$B002 select 1k CHR page @ $0000
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| if $B000=$03
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| and $B002=$01
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| then use page $13
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|
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|
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| $0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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| |$B000+2|$B004+6|$C000+2|$C004+6|$D000+2|$D004+6|$E000+2|$E004+6|
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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|
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|
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| --------------------------------------------------
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| --------------------------------------------------
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|
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|
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| VRC IRQs:
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| --------------------------
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| VRC IRQ logic is shared by VRC4, VRC6, and VRC7. IRQs for all of those mappers operate exactly the same way.
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| Therefore, this section applies to all of those mappers (other docs refer here).
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|
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| One thing in paticular to note with VRC4 that is different from VRC6, VRC7 is that the reload register is
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| split in two just as CHR regs are. $F000 specifies the low 4 bits of the reload value, and $F002 specfies
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| the high 4 bits. This only happens in VRC4. VRC6 and VRC7 have a single 8-bit register to specify the
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| reload value. The rest of this doc will refer to this reload value as a single register.
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|
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|
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| Notes:
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| --------------------------
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| VRC IRQs are unique in that they simulate a scanline counter, without actually counting scanlines. The IRQ
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| counter is actually a CPU cycle counter, with a prescaler that divides clocks by 113⅔ CPU cycles (one
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| NTSC scanline). This results in the IRQ counter being clocked once per scanline -- however unlike true
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| scanline counters, it will be clocked even when the PPU is inactive, and even during VBlank!
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|
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|
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|
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| Registers:
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| --------------------------
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|
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| There are 3 registers relevant to VRC IRQs. See respective mapper doc for which register corresponds to
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| which address:
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|
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| IRQ Reload: [IIII IIII]
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| This register specifies the counter reload value. It does not affect the counter itself.
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|
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| IRQ Control: [.... .MEA]
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| M = IRQ Mode (0=scanline mode, 1=CPU cycle mode)
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| E = Enable (0=disabled, 1=enabled)
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| A = Enable-on-acknowledge (see below)
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|
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| - If 'E' is written as set, the IRQ counter will be immediately reloaded with the
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| reload value, and the prescaler will be reset. IRQs will also be enabled.
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| - If 'E' is written as clear, the IRQ counter and prescaler are not changed, and IRQs are disabled.
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| - Any write to this register will acknowledge the IRQ.
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|
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|
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| IRQ Acknowledge: [.... ....]
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| Any write to this register will acknowledge the IRQ. In addition, the 'A' control bit is copied to the
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| 'E' control bit (enabling or disabling IRQs). No write to this register will change the state of the IRQ
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| counter or prescaler.
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|
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|
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| Operation:
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| --------------------------
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|
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| When in scanline mode ('M' control bit clear), a prescaler divides the passing CPU cycles by 114, 114, then
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| 113 (and then repeats that pattern). This averages 113 + 2/3 CPU cycles (1 NTSC scanline). When the
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| prescaler is reset, the sequence is reset, and it will be 114 CPU cycles until the next IRQ counter clock.
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|
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| A simple way to emulate prescaler behavior is to have it reset to 341, and subtract 3 every CPU cycle. When
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| it drops to or below 0, increment it by 341 and clock the IRQ counter once. This will produce the
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| 114,114,113 repeating pattern.
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|
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| When in cycle mode ('M' control bit set), the prescaler is effectively bypassed, and the IRQ counter gets
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| clocked every CPU cycle. In this mode, the prescaler remains unchanged by passing CPU cycles.
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|
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| If IRQs are disabled, neither the prescaler nor IRQ counter get clocked.
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|
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|
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| When the IRQ counter is clocked:
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| - If IRQ counter = $FF...
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| a) reload IRQ counter with reload value
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| b) trip IRQ
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|
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| - otherwise...
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| a) increment IRQ counter by 1
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