INES Mapper 018: Difference between revisions

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{{DEFAULTSORT:018}}[[Category:iNES Mappers]][[Category:in NesCartDB]][[Category:Expansion audio]][[Category:Mappers with cycle IRQs]]
{{DEFAULTSORT:018}}[[Category:iNES Mappers]][[Category:in NesCartDB]][[Category:Expansion audio]][[Category:Mappers with cycle IRQs]]
'''iNES Mapper 018''' represents the Jaleco SS88006 mapper used for ''Magic John'' (Japanese version of ''Totally Rad'') and a couple other games.
{{Infobox_iNES_mapper
|name=SS 88006
|company=Jaleco
|mapper=18
|nescartdbgames=15
|complexity=ASIC
|boards=JF-24, others
|pinout=Jaleco SS 88006 pinout
|prgmax=512K
|prgpage=8K + 8K + 8K + 8K fixed
|wrammax=8K
|wrampage=8K
|chrmax=256K
|chrpage=1Kx8
|mirroring=H, V, or 1, switchable
|busconflicts=No
|irq=Yes
}}
{{nesdbbox
|ines|18|iNES 018
}}
'''iNES Mapper 018''' represents the [[Jaleco SS 88006 pinout|Jaleco SS 88006 mapper]] used for ''Magic John'' (Japanese version of ''Totally Rad'') and about a dozen other games.


This mapper appears to be connected only to A12-A14, A0-A1, and D0-D3, so the PRG bank and CHR bank numbers are split over two adjacent mapper numbers.  Bits 0-3 are in the lower address of a pair (e.g. $xxx0 or $xxx2), and bits 4-7 are in the next higher address.
This mapper is connected only to A12-A14, A0-A1, and D0-D3, so the PRG bank and CHR bank numbers are split over two sequential addresses.  Bits 0-3 are in the lower address of a pair (e.g. $xxx0 or $xxx2), and bits 4-7 are in the next higher address.


<pre>
This mapper resembles a scrambled [[VRC4]].
$8000-1: PRG $8000
3210 3210
|||| ||||
++++-++++- Select 8192 byte PRG ROM bank in $8000-$9FFF


$8002-3: PRG $A000
== Banks ==
$9000-1: PRG $C000
* CPU $6000-$7FFF: 8 KB PRG RAM bank (optional)
(PRG $E000 is fixed to the last bank)
* CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
* CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
* CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
* CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
* PPU $0000-$03FF: 1 KiB switchable CHR bank
* PPU $0400-$07FF: 1 KiB switchable CHR bank
* PPU $0800-$0BFF: 1 KiB switchable CHR bank
* PPU $0C00-$0FFF: 1 KiB switchable CHR bank
* PPU $1000-$13FF: 1 KiB switchable CHR bank
* PPU $1400-$17FF: 1 KiB switchable CHR bank
* PPU $1800-$1BFF: 1 KiB switchable CHR bank
* PPU $1C00-$1FFF: 1 KiB switchable CHR bank


$A000-1: CHR $0000
== Registers ==
3210 3210
|||| ||||
++++-++++- Select 1024 byte CHR ROM bank in $0000-$03FF


$A002-3: CHR $0400
=== PRG Select 0 low($8000), high($8001) ===
$B000-1: CHR $0800
$B002-3: CHR $0C00
$C000-1: CHR $1000
$C002-3: CHR $1400
$D000-1: CHR $1800
$D002-3: CHR $1C00
</pre>


Nestopia also implements:
  $8000        $8001
  $9002: [..WR] W=1-can write to PRG RAM, 0-write protected; R=1-PRG RAM enabled for I/O at all
7  bit  0    7  bit  0
---------    ---------
  .... LLLL    .... ..HH
      ||||          ||
      ||||          ++- High 2 bits of 8 KiB PRG bank at CPU $8000
      ++++-------------- Low 4 bits


The IRQ counter is a 16-bit down counter.
=== PRG Select 1 and 2 ($8002-$9FFD) ===
Port $F001 controls how far the borrow propagates:
The other two PRG bank selects continue similarly:
If all counting bits wrap from $0 to $F, it doesn't modify the fixed bits before it but instead triggers an IRQ.
{| class="wikitable"
Writes to $F000 or $F001 acknowledge the IRQ.
! colspan=2|Write to CPU address
<pre>
! rowspan=2|8KB PRG bank affected
7654 3210  $F001: IRQ control
|-
    ||||
! (low 4 bits) !! (high 2 bits)
    |||+- Enable (0: pause; 1: count)
|-
    +++-- 0: Count down in bits 15-0 and hold no bits constant
| $8002 || $8003 || $A000-$BFFF
          1: Count down in bits 11-0 and hold bits 15-12 constant
|-
          2-3: Count down in bits 7-0 and hold bits 15-8 constant
| $9000 || $9001 || $C000-$DFFF
          4-7: Count down in bits 3-0 and hold bits 15-4 constant
|}


Alternate interpretation:
=== PRG RAM protect ($9002) ===
7  bit  0
---------
.... ..WR
        ||
        |+- PRG RAM chip enable (0: disable; 1: enable) (same as MMC3)
        +-- Write protection (0: deny writes; 1: allow writes) (opposite MMC3)


7654 3210 $F001: IRQ control
=== CHR Select 0 low($A000), high($A001) ===
    ||||
  $A000        $A001
    |||+- Enable (0: pause; 1: count)
  7  bit  0    7  bit  0
    ||+-- Hold bits 15-12 constant
---------    ---------
    |+--- Hold bits 15-8 constant
.... LLLL    .... HHHH
    +---- Hold bits 15-4 constant
      ||||        ||||
</pre>
      ||||         ++++- High 4 bits of 1 KiB CHR bank at PPU $0000
This counter uses a reload value.
      ++++-------------- Low 4 bits
All bits are reloaded, even the ones held constant.
*$E000: Set bits 3-0 of counter
*$E001: Set bits 7-4 of counter
*$E002: Set bits 11-8 of counter
*$E003: Set bits 15-12 of counter


=== CHR Selects 1…7 ($A002-$DFFF) ===
The other seven CHR bank selects continue similarly:
{| class="wikitable"
! colspan=2|Write to CPU address
! rowspan=2|1KB CHR bank affected
|-
! (low 4 bits) !! (high 4 bits)
|-
| $A002 || $A003 || $0400-$07FF
|-
| $B000 || $B001 || $0800-$0BFF
|-
| $B002 || $B003 || $0C00-$0FFF
|-
| $C000 || $C001 || $1000-$13FF
|-
| $C002 || $C003 || $1400-$17FF
|-
| $D000 || $D001 || $1800-$1BFF
|-
| $D002 || $D003 || $1C00-$1FFF
|}
=== IRQ reload value ($E000-$EFFF) ===
The four registers here represent a 16-bit reload value, split into four four-bit numbers, least significant four bits first.
=== IRQ reload ($F000-$FFFC) ===
Any write to this register will immediately reload the IRQ counter from the above reload value and acknowledge the IRQ.
=== IRQ counter size ($F001-$FFFD) ===
7  bit  0
---------
.... FETC
      ||||
      |||+- 1: Enable counting
      ||+-- 1: Don't propagate counter borrow to bit 12; instead assert IRQ
      |+--- 1: Don't propagate counter borrow to bit 8; instead assert IRQ
      +---- 1: Don't propagate counter borrow to bit 4; instead assert IRQ
F overrides E overrides T. If none are set, the counter is 16 bits wide.
Writes to this register also acknowledge the IRQ.
When enabled, the counter counts down.
=== Mirroring Control ($F002-$FFFE) ===
7  bit  0
---------
.... ..MM
        ||
        ++-- 0: Horizontal (A11)
            1: Vertical (A10)
            2: 1scA (Ground)
            3: 1scB (Vcc)
=== Expansion sound ($F003-$FFFF) ===
Some games also have a µPD7755C or µPD7756C ADPCM sound IC. If so,
Some games also have a µPD7755C or µPD7756C ADPCM sound IC. If so,
*$F003: Start playing sound specified by ''upper 6 bits''
7  bit  0
---------
NNNN NNRS
|||| ||||
|||| |||+-- 1: Assert (drive low) RESET on the ADPCM sound IC. 0: deassert (drive high)
|||| ||+--- 1: Assert START on the ADPCM sound IC. 0: deassert
++++-++---- Which sample to start, if START becomes asserted while RESET is deasserted.
           
This is the same audio playback IC used in other Jaleco mappers, with the same timing constraints.
RESET must be asserted for at least 34 cycles to be assured of stopping playback.
START must be de-asserted before the sample finishes playback, or else a random sample (depending on the current contents of the data bus) will start playing.
START will be ignored until 23 cycles after RESET is deasserted.


== Disch's Notes ==


   Here are Disch's original notes:
   Here are Disch's original notes:

Latest revision as of 21:48, 14 September 2020

SS 88006
Company Jaleco
Games 15 in NesCartDB
Complexity ASIC
Boards JF-24, others
Pinout Jaleco SS 88006 pinout
PRG ROM capacity 512K
PRG ROM window 8K + 8K + 8K + 8K fixed
PRG RAM capacity 8K
PRG RAM window 8K
CHR capacity 256K
CHR window 1Kx8
Nametable mirroring H, V, or 1, switchable
Bus conflicts No
IRQ Yes
Audio No
iNES mappers 018
NESCartDB
iNES 018

iNES Mapper 018 represents the Jaleco SS 88006 mapper used for Magic John (Japanese version of Totally Rad) and about a dozen other games.

This mapper is connected only to A12-A14, A0-A1, and D0-D3, so the PRG bank and CHR bank numbers are split over two sequential addresses. Bits 0-3 are in the lower address of a pair (e.g. $xxx0 or $xxx2), and bits 4-7 are in the next higher address.

This mapper resembles a scrambled VRC4.

Banks

  • CPU $6000-$7FFF: 8 KB PRG RAM bank (optional)
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
  • CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
  • CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
  • PPU $0000-$03FF: 1 KiB switchable CHR bank
  • PPU $0400-$07FF: 1 KiB switchable CHR bank
  • PPU $0800-$0BFF: 1 KiB switchable CHR bank
  • PPU $0C00-$0FFF: 1 KiB switchable CHR bank
  • PPU $1000-$13FF: 1 KiB switchable CHR bank
  • PPU $1400-$17FF: 1 KiB switchable CHR bank
  • PPU $1800-$1BFF: 1 KiB switchable CHR bank
  • PPU $1C00-$1FFF: 1 KiB switchable CHR bank

Registers

PRG Select 0 low($8000), high($8001)

  $8000        $8001
7  bit  0    7  bit  0
---------    ---------
.... LLLL    .... ..HH
     ||||           ||
     ||||           ++- High 2 bits of 8 KiB PRG bank at CPU $8000
     ++++-------------- Low 4 bits

PRG Select 1 and 2 ($8002-$9FFD)

The other two PRG bank selects continue similarly:

Write to CPU address 8KB PRG bank affected
(low 4 bits) (high 2 bits)
$8002 $8003 $A000-$BFFF
$9000 $9001 $C000-$DFFF

PRG RAM protect ($9002)

7  bit  0
---------
.... ..WR
       ||
       |+- PRG RAM chip enable (0: disable; 1: enable) (same as MMC3)
       +-- Write protection (0: deny writes; 1: allow writes) (opposite MMC3)

CHR Select 0 low($A000), high($A001)

  $A000        $A001
7  bit  0    7  bit  0
---------    ---------
.... LLLL    .... HHHH
     ||||         ||||
     ||||         ++++- High 4 bits of 1 KiB CHR bank at PPU $0000
     ++++-------------- Low 4 bits

CHR Selects 1…7 ($A002-$DFFF)

The other seven CHR bank selects continue similarly:

Write to CPU address 1KB CHR bank affected
(low 4 bits) (high 4 bits)
$A002 $A003 $0400-$07FF
$B000 $B001 $0800-$0BFF
$B002 $B003 $0C00-$0FFF
$C000 $C001 $1000-$13FF
$C002 $C003 $1400-$17FF
$D000 $D001 $1800-$1BFF
$D002 $D003 $1C00-$1FFF

IRQ reload value ($E000-$EFFF)

The four registers here represent a 16-bit reload value, split into four four-bit numbers, least significant four bits first.

IRQ reload ($F000-$FFFC)

Any write to this register will immediately reload the IRQ counter from the above reload value and acknowledge the IRQ.

IRQ counter size ($F001-$FFFD)

7  bit  0
---------
.... FETC
     ||||
     |||+- 1: Enable counting 
     ||+-- 1: Don't propagate counter borrow to bit 12; instead assert IRQ
     |+--- 1: Don't propagate counter borrow to bit 8; instead assert IRQ
     +---- 1: Don't propagate counter borrow to bit 4; instead assert IRQ

F overrides E overrides T. If none are set, the counter is 16 bits wide.

Writes to this register also acknowledge the IRQ.

When enabled, the counter counts down.

Mirroring Control ($F002-$FFFE)

7  bit  0
---------
.... ..MM
       ||
       ++-- 0: Horizontal (A11)
            1: Vertical (A10)
            2: 1scA (Ground)
            3: 1scB (Vcc)

Expansion sound ($F003-$FFFF)

Some games also have a µPD7755C or µPD7756C ADPCM sound IC. If so, 

7  bit  0
---------
NNNN NNRS
|||| ||||
|||| |||+-- 1: Assert (drive low) RESET on the ADPCM sound IC. 0: deassert (drive high)
|||| ||+--- 1: Assert START on the ADPCM sound IC. 0: deassert
++++-++---- Which sample to start, if START becomes asserted while RESET is deasserted.

This is the same audio playback IC used in other Jaleco mappers, with the same timing constraints. RESET must be asserted for at least 34 cycles to be assured of stopping playback. START must be de-asserted before the sample finishes playback, or else a random sample (depending on the current contents of the data bus) will start playing. START will be ignored until 23 cycles after RESET is deasserted.

Disch's Notes

 Here are Disch's original notes:
 ========================
 =  Mapper 018          =
 ========================
 
 
 Example Games:
 --------------------------
 The Lord of King
 Magic John
 Pizza Pop
 
 
 Registers:
 ---------------------------
 
 Range,Mask:   $8000-FFFF, $F003
 
   $800x,$900x:  [.... PPPP]  PRG Regs
   $A00x-$D00x:  [.... CCCC]  CHR Regs
   $E00x:  [.... IIII]  IRQ Reload value
   $F000:  [.... ....]  IRQ Reset
   $F001:  [.... SSSE]  IRQ Control
      S = Size of IRQ counter
      E = Enable
 
   $F002:  [.... ..MM]  Mirroring
      %00 = Horz
      %01 = Vert
      %10 = 1ScA
      %11 = 1ScB
 
 
 CHR Setup:
 ---------------------------
 
 Only low 4 bits of written value significant [.... CCCC]
 
 2 regs combined to get an 8-bit page number
 
 $x000 or $x002 are the low 4 bits
 $x001 or $x003 are the high 4 bits
 
 
       $0000   $0400   $0800   $0C00   $1000   $1400   $1800   $1C00 
     +-------+-------+-------+-------+-------+-------+-------+-------+
     |$A000+1|$A002+3|$B000+1|$B002+3|$C000+1|$C002+3|$D000+1|$D002+3|
     +-------+-------+-------+-------+-------+-------+-------+-------+
 
 
 PRG Setup:
 ---------------------------
 
 Same as CHR, $x000 low, $x001 high
 
       $8000   $A000   $C000   $E000 
     +-------+-------+-------+-------+
     |$8000+1|$8002+3|$9000+1| { -1} |
     +-------+-------+-------+-------+
 
 
 IRQ:
 ---------------------------
 
 16-bit IRQ Reload value is set via regs $E00x.  $E000 sets the low 4 bits, $E003 sets the high 4 bits.
 
 When enabled, the IRQ counter counts down every CPU cycle.  When it wraps, an IRQ is generated.
 
 The 'S' bits in the control reg determine the size of the IRQ counter.  It can be 4, 8, 12, or 16 bits wide:
 
   %000 = 16 bits wide
   %001 = 12 bits wide
   %01x = 8 bits wide
   %1xx = 4 bits wide
 
 If the counter is less than 16 bits, the high bits are not altered by IRQ counter clocking; they retain their
 value.
 
 Example:  if the IRQ counter contains $1232, and is in 4-bit mode, it counts like so:
 
   $1232
   $1231
   $1230
   $123F  <--- IRQ here
   $123E
    ...
 
 
 Any write to the reset reg ($F000) will copy the 16-bit reload value into the IRQ counter (full 16 bits are
 copied, regardless of current 'S' value).
 
 Any write to $F000 or $F001 will acknowledge the IRQ.


See also

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