9112 pinout: Difference between revisions
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(fixes, and same style as rest of pinouts on wiki) |
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(f) PPU A12 -> |02 39| -> CHR A16 (r) | (f) PPU A12 -> |02 39| -> CHR A16 (r) | ||
(f) PPU A11 -> |03 38| -> CHR A11 (r) | (f) PPU A11 -> |03 38| -> CHR A11 (r) | ||
(f) PPU A10 -> |04 37| | (f) PPU A10 -> |04 37| -> PRG RAM /WE (w) ? | ||
(r) CHR A13 <- |05 36| | (r) CHR A13 <- |05 36| -> PRG RAM +CE (w) ? | ||
(r) CHR A14 <- |06 35| <- CPU D3 (fr) | (r) CHR A14 <- |06 35| <- CPU D3 (fr) | ||
(r) CHR A12 <- |07 34| <- CPU D2 (fr) | (r) CHR A12 <- |07 34| <- CPU D2 (fr) | ||
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(r) CHR A15 <- |09 32| <- CPU D1 (fr) | (r) CHR A15 <- |09 32| <- CPU D1 (fr) | ||
(r) CHR A17 <- |10 31| <- CPU D5 (fr) | (r) CHR A17 <- |10 31| <- CPU D5 (fr) | ||
(f) /IRQ -> |11 30| <- CPU D0 (fr) | |||
(f) /ROMSEL <- |12 29| <- CPU D6 (fr) | |||
(f) R/W -> |13 28| <- CPU A0 (fr) | (f) R/W -> |13 28| <- CPU A0 (fr) | ||
(r) PRG A15 <- |14 27| <- CPU D7 (fr) | (r) PRG A15 <- |14 27| <- CPU D7 (fr) | ||
(r) PRG A13 <- |15 26| | (r) PRG A13 <- |15 26| -> PRG RAM /CE (w) ? | ||
(f) CPU A14 -> |16 25| | (f) CPU A14 -> |16 25| <- M2 (f) | ||
(r) PRG A16 <- |17 24| -> PRG /CE (r) | (r) PRG A16 <- |17 24| -> PRG /CE (r) | ||
(r) PRG A14 <- |18 23| ?? | (r) PRG A14 <- |18 23| ?? | ||
| Line 23: | Line 23: | ||
GND -- |20 21| <- CPU A13 (f) | GND -- |20 21| <- CPU A13 (f) | ||
'------' | '------' | ||
ps.: Pinout VERY similar to OEM MMC3. | |||
PRG RAM pins needs confirmation. | |||
== References == | == References == | ||
*[http://forums.nesdev.org/viewtopic.php?p=156990#p156990 BBS] | *[http://forums.nesdev.org/viewtopic.php?p=156990#p156990 BBS] | ||
[[Category:Pinouts]] | [[Category:Pinouts]] | ||
Revision as of 20:56, 23 February 2016
MMC3 clone, model 9112
.--\/--.
(r) CHR A10 <- |01 40| -- VCC
(f) PPU A12 -> |02 39| -> CHR A16 (r)
(f) PPU A11 -> |03 38| -> CHR A11 (r)
(f) PPU A10 -> |04 37| -> PRG RAM /WE (w) ?
(r) CHR A13 <- |05 36| -> PRG RAM +CE (w) ?
(r) CHR A14 <- |06 35| <- CPU D3 (fr)
(r) CHR A12 <- |07 34| <- CPU D2 (fr)
(f) CIRAM A10 <- |08 33| <- CPU D4 (fr)
(r) CHR A15 <- |09 32| <- CPU D1 (fr)
(r) CHR A17 <- |10 31| <- CPU D5 (fr)
(f) /IRQ -> |11 30| <- CPU D0 (fr)
(f) /ROMSEL <- |12 29| <- CPU D6 (fr)
(f) R/W -> |13 28| <- CPU A0 (fr)
(r) PRG A15 <- |14 27| <- CPU D7 (fr)
(r) PRG A13 <- |15 26| -> PRG RAM /CE (w) ?
(f) CPU A14 -> |16 25| <- M2 (f)
(r) PRG A16 <- |17 24| -> PRG /CE (r)
(r) PRG A14 <- |18 23| ??
(r) PRG A18 <- |19 22| -> PRG A17 (r)
GND -- |20 21| <- CPU A13 (f)
'------'
ps.: Pinout VERY similar to OEM MMC3.
PRG RAM pins needs confirmation.
