Namco 163 audio: Difference between revisions

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The [[Namco 163]] offers up to 8 additional sound channels that play wavetable samples while the [[iNES Mapper 210|175 and 340]] do not. Each waveform can be of a configurable length, and each channel has linear volume control. It has $80 bytes of sound RAM shared by channel registers and wavetable samples; at least $40 bytes are dedicated to samples, with more available if not all channels are used.
The [[Namco 163]] offers up to 8 additional sound channels that play wavetable samples while the [[iNES Mapper 210|175 and 340]] do not. Each waveform can be of a configurable length, and each channel has linear volume control. It has $80 bytes of sound RAM shared by channel registers and wavetable samples; at least $40 bytes are dedicated to samples, with more available if not all channels are used.


Like the Ensoniq DOC in the Apple IIGS, the chip is unable to clock every channel at once, so it cycles though channels, updating one every 15 CPU cycles. Because of this, the chip allows the game to configure the number of enabled channels.  When fewer channels are enabled, the channels are clocked more often, allowing for higher tones with longer, more detailed waveforms. When more channels are enabled, clocking slows down since each channel has to wait its turn, resulting in lower tones and a high-pitched whining noise at the switching frequency. Most N163 games used only 4 channels.
The chip is unable to clock every channel at once, so it cycles though channels, updating one every 15 CPU cycles. Because of this, the chip allows the game to configure the number of enabled channels.  When fewer channels are enabled, the channels are clocked more often, allowing for higher tones with longer, more detailed waveforms. When more channels are enabled, clocking slows down since each channel has to wait its turn, resulting in lower tones and a high-pitched whining noise at the switching frequency. Most games using this IC used only 4 channels.


== Registers ==
== Registers ==
Line 12: Line 12:
  .SPP PPPP
  .SPP PPPP
   ||| ||||
   ||| ||||
   |++-++++- Select 8KB page of PRG-ROM at $8000
   |++-++++- Select 8KB page of PRG-ROM at $8000-$9FFF
   +-------- Disables sound if set.
   +-------- Disables sound if set.


Sound is enabled on the N163 by writing a clear bit 6 to this register (0 is sufficient).
Sound is enabled on the 163 by writing a clear bit 6 to this register (0 is sufficient).


=== Address Port ($F800-$FFFF) ===
=== Address Port ($F800-$FFFF) ===
Line 26: Line 26:
  +--------- Auto-increment
  +--------- Auto-increment


Writing to this register sets the internal address.  If the 'I' bit is set, the address will increment on writes and reads to the Data Port ($4800), wrapping $7F->$00 (address is 7 bits wide)
Writing to this register sets the internal address to write to or read from.  If the 'I' bit is set, the address will increment on writes and reads to the Data Port ($4800), wrapping $7F->$00 (address is 7 bits wide).  Note that these auto-increments are subject to the DPCM [[DMA]] multiple-read bug that is well-known for affecting [[Controller reading code|controller reads]].


=== Data Port ($4800-$4FFF) ===
=== Data Port ($4800-$4FFF) ===
Line 36: Line 36:
  ++++-++++- Data
  ++++-++++- Data


This Port accesses the N163's internal $80 bytes of sound RAM.  Which of the $80 bytes is determined by the Address register ($F800).  When read, the appropriate byte is returned.  When written, the appropriate byte is set.
This Port accesses the 163's internal $80 bytes of sound RAM.  Which of the $80 bytes is determined by the Address register ($F800).  When read, the appropriate byte is returned.  When written, the appropriate byte is set.


This RAM is used primarily for wavetables.  The sound channel control registers are also set by writing to certain addresses in sound RAM:
This RAM is used primarily for wavetables.  The sound channel control registers are also set by writing to certain addresses in sound RAM:
Line 52: Line 52:
  7  bit  0
  7  bit  0
  ---------
  ---------
  FFFF FFFF
  PPPP PPPP
  |||| ||||
  |||| ||||
  ++++-++++- Low 8 bits of Phase
  ++++-++++- Low 8 bits of Phase
Line 68: Line 68:
  7  bit  0
  7  bit  0
  ---------
  ---------
  FFFF FFFF
  PPPP PPPP
  |||| ||||
  |||| ||||
  ++++-++++- Middle 8 bits of Phase
  ++++-++++- Middle 8 bits of Phase
Line 80: Line 80:
  |||| ||++- High 2 bits of Frequency
  |||| ||++- High 2 bits of Frequency
  ++++-++--- Length of waveform ((64-L)*4 4-bit samples)
  ++++-++--- Length of waveform ((64-L)*4 4-bit samples)
Equivalently, the waveform length = <code>256 - %LLLLLL00</code> samples.
The Namco 129 was never released with a game that used audio. However, on the Namco 129 this register instead only encodes length, supporting any length of waveform and not only multiple of 4 samples. In exchange, the high 2 bits of frequency can't be configured and are effectively always 0.


==== Sound RAM $7D - High Phase ====
==== Sound RAM $7D - High Phase ====
Line 85: Line 89:
  7  bit  0
  7  bit  0
  ---------
  ---------
  FFFF FFFF
  PPPP PPPP
  |||| ||||
  |||| ||||
  ++++-++++- High 8 bits of Phase
  ++++-++++- High 8 bits of Phase
Line 146: Line 150:
For a visual example, assume you have the following sound RAM:
For a visual example, assume you have the following sound RAM:


  $00:    00 00 00 A8 EC FE FF FF EE AC 57 13 01 00 00 11
  $00:    00 00 00 A8 DC EE FF FF EF DE AC 58 23 11 00 00
  $10:    53 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  $10:    10 21 53 00 00 00 00 00 00 00 00 00 00 00 00 00


And assume a channel has a 'A' value of $06, and a 'L' value of $39.  That channel's waveform would be a sine wave, looking like the following:
And assume a channel has an 'A' value of $06, and an 'L' value of $38.  That channel's waveform would be a sine wave, looking like the following:


  F-     *****
  F -       *****
  E-   **    **
  E -     **    **
  D-
  D -   *        *
  C- *         *
  C -   *           *
  B-
  B -
  A- *           *
  A - *             *
  9-
  9 -  
  8-*
  8 - *              *
  7-             *
  7 -  
  6-
  6 -
  5-               *           *
  5 -                 *             *
  4-
  4 -
  3-               *         *
  3 -                   *           *
  2-
  2 -                   *        *
  1-                 **    **
  1 -                     **    **
  0-                   *****
  0 -                       *****


== Channel Update ==
== Channel Update ==


The N163 does not internally mix its channels. Instead, each channel is output one at a time. It takes the N163 exactly 15 CPU cycles to update and output one channel. When multiple channels are used it will cycle between them. With 6 or fewer channels, the time to update all channels is a rate faster than any audible frequency, and the difference between this serial output and mixing cannot be heard, but for 8 channels it creates a very loud and apparent noise at the update rate. For a Famicom through RF output, this noise is attenuated during demodulation (which performs a lowpass filter), but through A/V output to a TV that does not filter high frequencies, it can be very unpleasant. Only two games used all 8 channels: ''King of Kings'' and ''Erika to Satoru no Yume Bouken''.
Namco's 163 does not internally mix its channels. Instead, each channel is output one at a time. It takes exactly 15 CPU cycles to update and output one channel. When multiple channels are used it will cycle between them. With 6 or fewer channels, the time to update all channels is a rate faster than any audible frequency, and the difference between this serial output and mixing cannot be heard, but for 8 channels it creates a very loud and apparent noise at the update rate. For a Famicom through RF output, this noise is attenuated during demodulation (which performs a lowpass filter), but through A/V output to a TV that does not filter high frequencies, it can be very unpleasant. Only two games used all 8 channels: ''King of Kings'' and ''Erika to Satoru no Yume Bouken''.


{| class="tabular"
{| class="tabular"
! Channels || Update Rate
! Channels<br/>Enabled || Update Rate<br/>(NTSC) || Update Rate<br/>(PAL)
|-
|-
| 1 || 119318 Hz
| 1 || 119.318 kHz || 110.840 kHz
|-
|-
| 2 || 59659 Hz
| 2 || 59.659 kHz || 55.420 kHz
|-
|-
| 3 || 39773 Hz
| 3 || 39.773 kHz || 36.947 kHz
|-
|-
| 4 || 29830 Hz
| 4 || 29.830 kHz || 27.710 kHz
|-
|-
| 5 || 23864 Hz
| 5 || 23.864 kHz || 22.168 kHz
|-
|-
| 6 || 19886 Hz
| 6 || 19.886 kHz || 18.473 kHz
|-
|-
| 7 || 17045 Hz
| 7 || 17.045 kHz || 15.834 kHz
|-
|-
| 8 || 14915 Hz
| 8 || 14.915 kHz || 13.855 kHz
|}
|}


The following is a speculative version of a single channel update, occurring every 15 CPU cycles:
The following is a speculative version of a single channel update, occurring every 15 CPU cycles:


  * ''w''[$80] = N163 internal memory
  * ''w''[$80] = the 163's internal memory
  * ''sample''(x) = (''w''[x/2] >> ((x&1)*4)) & $0F
  * ''sample''(x) = (''w''[x/2] >> ((x&1)*4)) & $0F
  * ''phase'' = (''w''[$7D] << 16) + (''w''[$7B] << 8) + ''w''[$79]
  * ''phase'' = (''w''[$7D] << 16) + (''w''[$7B] << 8) + ''w''[$79]
Line 217: Line 221:
  c = number of channels
  c = number of channels
  p = 18-bit frequency value
  p = 18-bit frequency value
  n = CPU clock rate (~1789772 Hz)
  n = CPU clock rate (≈1789773 Hz)
 
  f = (n * p) / (15 * 65536 * l * c)
  f = (n * p) / (15 * 65536 * l * c)


== Mixing ==
== Mixing ==


The relative volume of the N163 unit various from game to game, unfortunately.
The relative volume of the IC varies from game to game, unfortunately. The following samples have been recorded using various test programs.
 
An N163 with a single channel enabled is somewhere between ~3.6x and ~8.5x as loud as the APU square at max volume. The two 8-channel games have a louder mix, probably to compensate for the quieter volume when more channels are enabled. Some 4-channel games have a quieter mix. The polarity of the N163 is reversed from the 2A03.


The volume comparison measured on various cartridges:
(Values in parentheses are estimated based on listening/balance.)
{| class="tabular"
{| class="tabular"
! 4-Channel Game  || Volume || Samples
! colspan="4" | Difference between loudest APU square and loudest N163 square in 1-channel mode (dB)
|-
|-
| Final Lap        || 3.6x  || 1
! Game
! [http://forums.nesdev.org/viewtopic.php?f=2&t=16910#p222765 NewRisingSun]
! [http://forums.nesdev.org/viewtopic.php?f=2&t=16910&start=30#p222880 jrlepage]
! [http://forums.nesdev.org/viewtopic.php?f=2&t=16910&start=15#p222873 Rainwarrior]
|-
|-
| Mappy Kids      || (~6x)  || 0
|Final Lap                      || 12.7 || 11.2 ||
|-
|-
| Megami Tensei II || 4.0x  || 1
|Sangokushi II: Haou no Tairiku || 12.9 ||      ||
|-
|-
| Namco Classic 2  || (~6x)  || 0
|Megami Tensei II              || 13.0 || 11.9 ||
|-
|-
| Rolling Thunder || 6.5x  || 2
|Rolling Thunder               || 16.9 || 16.0 || 16.9
|-
|-
| Sangokushi      || (~6x)  || 0
|King of Kings                  || 18.0 || 17.3 ||
|-
|-
| Sangokushi 2    || (~4x)  || 0
|Mappy Kids                    || 18.6 ||      ||
|-
|-
! 8-Channel Game                || Volume || Samples
|Erika to Satoru no Yume Bouken || 18.8 ||     || 18.9
|-
|-
| Erika to Satoru no Yumebouken || 8.5x  || 1
|Youkai Douchuu-ki              || 18.9 ||      ||
|-
|-
| King of Kings                || 7.3x  || 1
|Sangokushi: Chuugen no Hasha  || 19.5 ||      ||
|}
|}


Since the mix appears to be arbitrarily chosen per-game, how to handle this is a difficult choice for an emulator author. It should probably be adjustable. You may choose to simply boost the volume when 8-channels are used. You may try to use a value in between (~6.0x sounds well for all games except Final Lap and Sangokushi 2). You may keep a table of N163 games and their volumes (ignoring potential homebrew), though more data needs to be collected . It should be noted that the 8-channel games do not significantly use the 2A03 for music, except the noise channel, so an accurate mix may be less important.
Based on these measurements, the following submappers were allocated:
{{:INES Mapper 019/Submapper table}}


Because the high frequency generated by the channel cycling can be unpleasant, and emulation of high frequency audio can be difficult, it is often preferred to simply sum the channel outputs, and divide the output volume by the number of channels. To compensate for less drop in apparent volume once the switching frequency crosses the threshold of audibility, it may be desired to slightly increase the volume for >5 channels (perhaps always dividing the output by 6 for 6, 7 or 8 channels).
Because the high frequency generated by the channel cycling can be unpleasant, and emulation of high frequency audio can be difficult, it is often preferred to simply sum the channel outputs, and divide the output volume by the number of active channels. For 6 channels or more, where the switching frequency crosses the threshold of audibility, this approximation will become slightly too loud as it fails to compensate for the transferred energy.


== References ==
== References ==


*[[Namcot 163 family pinout]] - diagram of the chip
*[http://nesdev.org/namco106.txt Namcot 106 Mapper Information] by Goroh, ZW4, nori
*[http://nesdev.org/namco106.txt Namcot 106 Mapper Information] by Goroh, ZW4, nori
*[http://kevtris.org/nes/nsfspec.txt NES Music Format Spec] by Kevin Horton, N106 info by Mamiya
*[http://kevtris.org/nes/nsfspec.txt NES Music Format Spec] by Kevin Horton, N106 info by Mamiya

Latest revision as of 01:17, 25 August 2024

The Namco 163 offers up to 8 additional sound channels that play wavetable samples while the 175 and 340 do not. Each waveform can be of a configurable length, and each channel has linear volume control. It has $80 bytes of sound RAM shared by channel registers and wavetable samples; at least $40 bytes are dedicated to samples, with more available if not all channels are used.

The chip is unable to clock every channel at once, so it cycles though channels, updating one every 15 CPU cycles. Because of this, the chip allows the game to configure the number of enabled channels. When fewer channels are enabled, the channels are clocked more often, allowing for higher tones with longer, more detailed waveforms. When more channels are enabled, clocking slows down since each channel has to wait its turn, resulting in lower tones and a high-pitched whining noise at the switching frequency. Most games using this IC used only 4 channels.

Registers

Sound Enable ($E000-E7FF)

7  bit  0
---- ----
.SPP PPPP
 ||| ||||
 |++-++++- Select 8KB page of PRG-ROM at $8000-$9FFF
 +-------- Disables sound if set.

Sound is enabled on the 163 by writing a clear bit 6 to this register (0 is sufficient).

Address Port ($F800-$FFFF)

7  bit  0   (write only)
---- ----
IAAA AAAA
|||| ||||
|+++-++++- Address
+--------- Auto-increment

Writing to this register sets the internal address to write to or read from. If the 'I' bit is set, the address will increment on writes and reads to the Data Port ($4800), wrapping $7F->$00 (address is 7 bits wide). Note that these auto-increments are subject to the DPCM DMA multiple-read bug that is well-known for affecting controller reads.

Data Port ($4800-$4FFF)

7  bit  0   (read / write)
---- ----
DDDD DDDD
|||| ||||
++++-++++- Data

This Port accesses the 163's internal $80 bytes of sound RAM. Which of the $80 bytes is determined by the Address register ($F800). When read, the appropriate byte is returned. When written, the appropriate byte is set.

This RAM is used primarily for wavetables. The sound channel control registers are also set by writing to certain addresses in sound RAM:

Sound RAM $78 - Low Frequency

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Low 8 bits of Frequency

Sound RAM $79 - Low Phase

7  bit  0
---------
PPPP PPPP
|||| ||||
++++-++++- Low 8 bits of Phase

Sound RAM $7A - Mid Frequency

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Middle 8 bits of Frequency

Sound RAM $7B - Mid Phase

7  bit  0
---------
PPPP PPPP
|||| ||||
++++-++++- Middle 8 bits of Phase

Sound RAM $7C - High Frequency and Wave Length

7  bit  0
---------
LLLL LLFF
|||| ||||
|||| ||++- High 2 bits of Frequency
++++-++--- Length of waveform ((64-L)*4 4-bit samples)

Equivalently, the waveform length = 256 - %LLLLLL00 samples.

The Namco 129 was never released with a game that used audio. However, on the Namco 129 this register instead only encodes length, supporting any length of waveform and not only multiple of 4 samples. In exchange, the high 2 bits of frequency can't be configured and are effectively always 0.

Sound RAM $7D - High Phase

7  bit  0
---------
PPPP PPPP
|||| ||||
++++-++++- High 8 bits of Phase

The high byte of the 24-bit phase value directly determines the current sample position of the channel. Every time a channel is updated, the 18-bit frequency value is added to the 24-bit phase accumulator, which is stored in these three registers.

The phase registers may be written to immediately set the phase of the wave. It is good practice to set the frequency to 0 before doing so.

Sound RAM $7E - Wave Address

7  bit  0
---------
AAAA AAAA
|||| ||||
++++-++++- Address of waveform (in 4-bit samples)

Sound RAM $7F - Volume

7  bit  0
---------
.CCC VVVV
 ||| ||||
 ||| ++++- Linear Volume
 +++------ Enabled Channels (1+C)

Note 'C' is available on register $7F ONLY. Those bits have no effect in other registers.

  • When C=0, only channel 8 enabled
  • When C=1, channels 8 and 7 enabled
  • When C=2, channels 8, 7, 6 enabled
  • etc...

Other Channels

Above Sound RAM register descriptions ($78-$7F) are for the 8th channel. The other 7 channels are accessed via the same pattern, but each 8 bytes before the last: 

Channel 8:  $78-$7F
Channel 7:  $70-$77
Channel 6:  $68-$6F
Channel 5:  $60-$67
Channel 4:  $58-$5F
Channel 3:  $50-$57
Channel 2:  $48-$4F
Channel 1:  $40-$47

Again note that the 'C' bits in the final register is only available at address $7F.

When channels are disabled, their registers are unused, and can be used for waveform data instead.

Waveform

Each enabled channel cycles through its waveform at a rate determined by the 18-bit frequency value 'F'. Each step in the waveform is 4-bits wide, and the number of steps is determined by the 'L' bits ((64-L)*4). Two samples are stored to a byte, which is little-endian (unlike the Game Boy's wavetable channel).

The 'A' bits dictate where in the internal sound RAM the waveform starts. 'A' is the address in 4-bit samples, therefore a value of $02 would be the low 4 bits of address $01. A value of $03 would be the high 4 bits of address $01.

For a visual example, assume you have the following sound RAM: 

$00:    00 00 00 A8 DC EE FF FF EF DE AC 58 23 11 00 00
$10:    10 21 53 00 00 00 00 00 00 00 00 00 00 00 00 00

And assume a channel has an 'A' value of $06, and an 'L' value of $38. That channel's waveform would be a sine wave, looking like the following: 

F -       *****
E -     **     **
D -    *         *
C -   *           *
B -
A -  *             *
9 - 
8 - *               *
7 - 
6 -
5 -                  *             *
4 -
3 -                   *           *
2 -                    *         *
1 -                     **     **
0 -                       *****

Channel Update

Namco's 163 does not internally mix its channels. Instead, each channel is output one at a time. It takes exactly 15 CPU cycles to update and output one channel. When multiple channels are used it will cycle between them. With 6 or fewer channels, the time to update all channels is a rate faster than any audible frequency, and the difference between this serial output and mixing cannot be heard, but for 8 channels it creates a very loud and apparent noise at the update rate. For a Famicom through RF output, this noise is attenuated during demodulation (which performs a lowpass filter), but through A/V output to a TV that does not filter high frequencies, it can be very unpleasant. Only two games used all 8 channels: King of Kings and Erika to Satoru no Yume Bouken.

Channels
Enabled		 Update Rate
(NTSC)		 Update Rate
(PAL)
1 119.318 kHz 110.840 kHz
2 59.659 kHz 55.420 kHz
3 39.773 kHz 36.947 kHz
4 29.830 kHz 27.710 kHz
5 23.864 kHz 22.168 kHz
6 19.886 kHz 18.473 kHz
7 17.045 kHz 15.834 kHz
8 14.915 kHz 13.855 kHz

The following is a speculative version of a single channel update, occurring every 15 CPU cycles: 

* w[$80] = the 163's internal memory
* sample(x) = (w[x/2] >> ((x&1)*4)) & $0F
* phase = (w[$7D] << 16) + (w[$7B] << 8) + w[$79]
* freq = ((w[$7C] & $03) << 16) + (w[$7A] << 8) + w[$78]
* length = 256 - (w[$7C] & $FC)
* offset = w[$7E]
* volume = w[$7F] & $0F

phase = (phase + freq) % (length << 16)
output = (sample(((phase >> 16) + offset) & $FF) - 8) * volume

The output will be held until the next channel update. The 24-bit phase value will be stored back into w[$7D/$7B/$79].

The sample value is biased by -8, meaning that a waveform value of 8 represents the centre voltage. This means that volume changes have no effect on a sample of 8, will tend negative if <8 and positive if >8.

Frequency

The wave position is driven by the high 8 bits of a 24-bit accumulator. Every 15 CPU clocks, one channel will add its 18-bit frequency to the accumulator. Because only one channel is updated per tick, the output frequency is thus divided by the number of channels enabled. 

f = wave frequency
l = wave length
c = number of channels
p = 18-bit frequency value
n = CPU clock rate (≈1789773 Hz)

f = (n * p) / (15 * 65536 * l * c)

Mixing

The relative volume of the IC varies from game to game, unfortunately. The following samples have been recorded using various test programs.

Difference between loudest APU square and loudest N163 square in 1-channel mode (dB)
Game NewRisingSun jrlepage Rainwarrior
Final Lap 12.7 11.2
Sangokushi II: Haou no Tairiku 12.9
Megami Tensei II 13.0 11.9
Rolling Thunder 16.9 16.0 16.9
King of Kings 18.0 17.3
Mappy Kids 18.6
Erika to Satoru no Yume Bouken 18.8 18.9
Youkai Douchuu-ki 18.9
Sangokushi: Chuugen no Hasha 19.5

Based on these measurements, the following submappers were allocated:

INES Mapper 019 submapper table
Submapper # Meaning Note
0 Default Expansion sound volume unspecified
1 Deprecated Internal 128b RAM is battery backed, no external PRG-RAM is present.

No expansion sound. (Equivalent to submapper 2 with 0 in PRG-NVRAM field.)

2 No expansion sound
3 N163 expansion sound: 11.0-13.0 dB louder than NES APU
4 N163 expansion sound: 16.0-17.0 dB louder than NES APU
5 N163 expansion sound: 18.0-19.5 dB louder than NES APU


Because the high frequency generated by the channel cycling can be unpleasant, and emulation of high frequency audio can be difficult, it is often preferred to simply sum the channel outputs, and divide the output volume by the number of active channels. For 6 channels or more, where the switching frequency crosses the threshold of audibility, this approximation will become slightly too loud as it fails to compensate for the transferred energy.

References

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