INES Mapper 019: Difference between revisions

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[[Category:iNES Mappers|019]][[Category:in NesCartDB|019]]
{{DEFAULTSORT:019}}[[Category:Mappers with CHR ROM and CHR RAM]]
{{Infobox_iNES_mapper
|name=Namco 129/163
|company=Namco
|mapper=19
|nescartdbgames=20
|boards=11xF0, 111F0S
|pinout=Namcot 163 family pinout
|complexity=ASIC
|prgmax=512K
|prgpage=8Kx3 + 8K fixed
|wrammax=8K
|wrampage=8K
|chrmax=256K
|chrpage=1Kx8 (PT) + 1Kx4 (NT)
|mirroring=arbitrary, up to 226 source nametables
|busconflicts=No
|irq=CPU cycle counter
|audio=[[Namco_163_audio|Yes]]
}}
'''iNES Mapper 019''' is used to denote Famicom boards bearing the '''Namco 129''' and '''Namco 163''' ASICs. These chips contain 128 bytes of internal RAM that can be used either for [[Namco 163 audio|expansion audio]] or, together with a battery, for 128 bytes of save RAM. Games may also come with the regular 8 KiB of additional battery-backed WRAM mapped into CPU address space at $6000-$7FFF.


Please refer to the notes at [[Namco 163]], which contain more recent research by Naruko.
In [[NES 2.0]], the 128 bytes of internal chip RAM are not included in the PRG-RAM and PRG-NVRAM fields. NES 2.0 Mapper 19 ROM images therefore either have:
* no battery and no WRAM: battery bit clear, PRG-RAM/PRG-NVRAM both set to zero.
* a battery but no WRAM: battery bit set, PRG-RAM/PRG-NVRAM both set to zero. The game writes its save data into the 128 byte internal RAM.
* a battery and WRAM: battery bit set, PRG-RAM set to zero and PRG-NVRAM set to 8192.
The NES 2.0 submapper is used to specify the mixing resistor that determines the relative volume of the expansion audio channels against the [[APU]]'s audio channels:
{{:INES Mapper 019/Submapper table}}


  Here are Disch's original notes: 
==Game list==
  ========================
{| class="wikitable sortable"
  =  Mapper 019          =
! Name !! Chip !! Battery !! WRAM !! Expansion Audio !! NES 2.0 Submapper
  =      + 210          =
|-
  ========================
|''Battle Fleet'' || 163 || Yes || No || No || 2
 
|-
  aka
|''Dragon Ninja'' || 163 || No || No || No || 2
  --------------------------
|-
  Namco 163
|''Digital Devil Story: Megami Tensei II'' || 163 || Yes || Yes || Yes || 3
 
|-
 
|''Dokuganryuu Masamune'' || 163 || Yes || No || No || 2
 
|-
  Example Games:
|''Erika to Satoru no Yume Bouken'' || 163 || No || No || Yes || 5
  --------------------------
|-
  Digital Devil Story - Megami Tensei 2  (019)
|''Famista '90'' || 163 || Yes || No || No || 2
  Final Lap                      (019)
|-
  Rolling Thunder (J)            (019)
|''Final Lap'' || 163 || No || No || Yes || 3
  Splatter House                (019)
|-
  Mappy Kids                    (019)
|''Hydlide 3: Yami kara no Houmonsha'' || 163 || Yes || No || No || 2
  Family Circuit '91            (210)
|-
  Wagyan Land 2,3                (210)
|''Juvei Quest'' || 163 || Yes || Yes || No || 2
  Dream Master                  (210)
|-
 
|''Kaijuu Monogatari'' || 163 || Yes || No || No || 2
 
|-
 
|''King of Kings'' || 163 || Yes || Yes || Yes || 5
  General Notes:
|-
  --------------------------
|''Mappy Kids'' || 163 || No || No || Yes || 5
  For a while, this mapper number was shared with 210.  Therefore, there are a lot of ROMs floating around that
|-
  are labelled as mapper 019 that are really mapper 210. 
|''Mindseeker'' || 163 || Yes || No || No || 2
 
|-
  Some games require CHR-RAM in addition to any CHR-ROM present.  I'm uncertain exactly how much, but giving
|''Namco Classic'' || 163 || No || No || No || 2
  them 8k seems to work.
|-
 
|''Namco Classic II'' || 163 || No || No || Yes || 3
  Mapper 019 sometimes has an additional 128 bytes of Sound RAM, which is used for waveform tables and sound
|-
  registers.  Kaijuu Monogatari uses this as battery backed SRAM.
|''Rolling Thunder'' || 163 || No || No || Yes || 4
 
|-
  The rest of the doc applies to both mapper numbers.  Differences between the two (mirroring and sound) will
|''Sangokushi: Chuugen no Hasha'' || 163 || Yes || Yes || Yes || 5
  be noted where appropriate.
|-
 
|''Sangokushi II: Haou no Tairiku'' || 163 || Yes || Yes || Yes || 3
 
|-
  Registers:
|''Star Wars'' || 129 || No || No || No || 2
  --------------------------
|-
 
|''Youkai Douchuuki'' || 163 || No || No || Yes || 5
  Range,Mask:  $4800-FFFF, $F800
|-
 
|}
  Writable and Readable:
 
    $4800: [DDDD DDDD]    Sound Data port (see Sound section for details)
== Banks ==
                            (mapper 019 only)
* CPU $6000-$7FFF: 8 KB PRG RAM bank, if WRAM is present
 
* CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
    $5000: [IIII IIII]    Low 8 bits of IRQ counter
* CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
    $5800: [EIII IIII]
* CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
        E = IRQ Enable (0=disabled, 1=enabled)
* CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
        I = High 7 bits of IRQ counter
* PPU $0000-$03FF: 1 KB switchable CHR bank
 
* PPU $0400-$07FF: 1 KB switchable CHR bank
 
* PPU $0800-$0BFF: 1 KB switchable CHR bank
 
* PPU $0C00-$0FFF: 1 KB switchable CHR bank
    $6000-7FFF:   mapped to PRG-RAM, not registers
* PPU $1000-$13FF: 1 KB switchable CHR bank
 
* PPU $1400-$17FF: 1 KB switchable CHR bank
  Writable only:
* PPU $1800-$1BFF: 1 KB switchable CHR bank
    $8000-B800:         CHR Regs
* PPU $1C00-$1FFF: 1 KB switchable CHR bank
    $C000-D800:         Mirroring Regs  (mapper 019 only)
* PPU $2000-$23FF: 1 KB switchable CHR bank
    $E000: [..PP PPPP]  PRG Reg 0 (8k @ $8000)
* PPU $2400-$27FF: 1 KB switchable CHR bank
    $E800: [HLPP PPPP]
* PPU $2800-$2BFF: 1 KB switchable CHR bank
        H = High CHR RAM Disable  (see CHR setup for details)
* PPU $2C00-$2FFF: 1 KB switchable CHR bank
        L = Low CHR RAM Disable
 
        P = PRG Reg 1 (8k @ A000)
These ASICs have the unusual ability to select the internal 2 KB nametable RAM as a CHR bank page, allowing it to be used as CHR RAM in combination with the existing CHR ROM.
 
 
    $F000:  [..PP PPPP]  PRG Reg 2 (8k @ $C000)
== Registers ==
 
The 163 has 19 registers within $4800-$5FFF and $8000-$FFFF. Each register occupies a range of $800 bytes, so $4800-$4FFF all refers to one register, $5000-$57FF all refers to another register, and so on.
    $F800:  [IAAA AAAA]  Sound Address (with auto-increment enable bit)
 
                        (See Sound section for details) (mapper 019 only)
=== Chip RAM Data Port ($4800-$4FFF) r/w ===
 
See [[Namco 163 audio]].
 
 
 
=== IRQ Counter (low) ($5000-$57FF) r/w ===
  PRG Setup:
7  bit  0
  --------------------------
---- ----
 
IIII IIII
        $8000  $A000  $C000  $E000  
|||| ||||
      +-------+-------+-------+-------+
++++-++++- Low 8 bits of IRQ counter
      | $E000 | $E800 | $F000 | { -1} |
 
      +-------+-------+-------+-------+
=== IRQ Counter (high) / IRQ Enable ($5800-$5FFF) r/w ===
 
7  bit  0
 
---- ----
  CHR Setup:
EIII IIII
  --------------------------
|||| ||||
 
|+++-++++- High 7 bits of IRQ counter
        $0000  $0400  $0800  $0C00  $1000  $1400  $1800  $1C00
+--------- IRQ Enable: (0: disabled; 1: enabled)
      +-------+-------+-------+-------+-------+-------+-------+-------+
 
      | $8000 | $8800 | $9000 | $9800 | $A000 | $A800 | $B000 | $B800 |
=== CHR and NT Select ($8000-$DFFF) w ===
      +-------+-------+-------+-------+-------+-------+-------+-------+
 
 
{| class="wikitable"
  Page numbers lower than $E0 will select CHR-ROM. Page numbers greater than or equal to $E0 will select
! Value CPU writes !! Behavior
  CHR-RAM (RAM page N - $E0)  *unless* CHR-RAM for the region is disabled via the appropriate bit in $E800.
|-
 
| $00-$DF || Always selects 1KB page of CHR-ROM
  $E800.6, when set, disables RAM selection for $0xxx ($8000-9800 will always select ROM)
|-
  $E800.7, when set, disables RAM selection for $1xxx ($A000-B800 will always select ROM)
| $E0-$FF || If enabled by bit in $E800, use the NES's internal nametables (even values for A, odd values for B)
 
|}
  CHR-RAM disable allows games to utilize all 256k of CHR-ROM. When CHR-RAM is enabled, only 224k can be
{| class="wikitable"
  accessed.
! Write to CPU address !! 1KB CHR bank affected !! Values ≥ $E0 denote NES NTRAM if
 
|-
 
| $8000-$87FF || $0000-$03FF || $E800.6 = 0
  Mirroring:
|-
  --------------------------
| $8800-$8FFF || $0400-$07FF || $E800.6 = 0
 
|-
  This section applies to mapper 019 only. 210 has hardwired mirroring
| $9000-$97FF || $0800-$0BFF || $E800.6 = 0
 
|-
    [ $C000 ][ $C800 ]
| $9800-$9FFF || $0C00-$0FFF || $E800.6 = 0
    [ $D000 ][ $D800 ]
|-
 
| $A000-$A7FF || $1000-$13FF || $E800.7 = 0
  Values less than $E0 select a CHR-ROM page for a NT. Values $E0 and up use NES's internal nametables
|-
  (low bit selects which).
| $A800-$AFFF || $1400-$17FF || $E800.7 = 0
 
|-
  Typical Examples:
| $B000-$B7FF || $1800-$1BFF || $E800.7 = 0
          $C000 $C800 $D000 $D800
|-
          -----------------------
| $B800-$BFFF || $1C00-$1FFF || $E800.7 = 0
  Horz:     $E0   $E0  $E1  $E1
|-
  Vert:    $E0  $E1  $E0  $E1
| $C000-$C7FF || $2000-$23FF || always
 
|-
 
| $C800-$CFFF || $2400-$27FF || always
 
|-
  IRQ Operation:
| $D000-$D7FF || $2800-$2BFF || always
  --------------------------
|-
 
| $D800-$DFFF || $2C00-$2FFF || always
  IRQs are driven by a 15-bit CPU cycle up-counter.  $5000 and $5800 are *direct* access to the IRQ counter
|}
  (they are not a reload value). Games can also read back the real-time state of the IRQ counter by reading
It is believed, but untested, that a game could add a normal SRAM and use it in lieu of the nametable RAM; if so, a game would be able to get 4-screen mirroring and many more pages of CHR-RAM.
  those regs.
 
 
=== PRG Select 1 ($E000-$E7FF) w ===
  When IRQs are enabled, the following occurs every CPU cycle:
7  bit  0
 
---- ----
  - If IRQ Counter = $7FFF
AMPP PPPP
    a) Trip IRQ
|||| ||||
 
||++-++++- Select 8KB page of PRG-ROM at $8000
  - otherwise...
  |+-------- Disable sound if set
    a) Increment IRQ counter by 1
+--------- Pin 22 (open collector) reflects the inverse of this value, unchanged by the address bus inputs.
 
 
  Reading/Writing $5000 or $5800 will acknowledge the pending IRQ.
If not battery backed, the internal sound RAM powers on in a random state, and similarly the N163 may power on with sound enabled. A short burst of sound due to these random settings may be heard at first power-on, before the game software manages to disable it.
 
 
 
=== PRG Select 2 / CHR-RAM Enable ($E800-$EFFF) w ===
  Sources on the behavior of this IRQ counter vary. Some say that the IRQ counter wraps from $7FFF to $0000,
7  bit  0
  and trips an IRQ only when it wraps -- however Sangokushi 2 polls $5800, and emulating IRQs that way results
  ---- ----
  in the game locking up shortly after it starts (once it sees that $5800 is not what it expects, it resets the
HLPP PPPP
  IRQ counter and loops)
|||| ||||
 
||++-++++- Select 8KB page of PRG-ROM at $A000
  Emulating the IRQ counter as above seems to work for every game out there -- although it probably isn't 100%
|+-------- Disable CHR-RAM at $0000-$0FFF
  accurate.
|            0: Pages $E0-$FF use NT RAM as CHR-RAM
 
  |            1: Pages $E0-$FF are the last $20 banks of CHR-ROM
 
  +--------- Disable CHR-RAM at $1000-$1FFF
 
              0: Pages $E0-$FF use NT RAM as CHR-RAM
 
              1: Pages $E0-$FF are the last $20 banks of CHR-ROM
  Sound:
 
  --------------------------
=== PRG Select 3 ($F000-$F7FF) w ===
 
7  bit  0
  Sound applies to mapper 019 only.  Mapper 210 has no extra sound.
---- ----
 
CDPP PPPP
  [[Namco 163 audio|N163]] has some pretty sweet expansion sound. And it's used in several games to boot!  (More than any other
|||| ||||
  expansion except for FDS)
||++-++++- Select 8KB page of PRG-ROM at $C000
 
  ++-------- PPU A12, A13 and these bits control pin 44
  The N163 has up to 8 additional sound channels, each which plays back a configurable waveform of variable
 
  length, as well as having full volume control for each channel.
Pin 44 is high if:
 
* PPU A13 is high and D is high
  There are 128 bytes of Sound RAM inside the N163 which is used to hold the waveform data, as well as sound
* PPU A13 is low and
  registers. This RAM is accessed by setting the desired address by writing to $F800, then writing the
** C or PPU A12 are high
  desired data to $4800.  $4800 is also readable.
 
 
=== Write Protect for External RAM AND Chip RAM Address Port ($F800-$FFFF) w ===
    $F800:  [IAAA AAAA]
7  bit  0
      I = Auto-increment flag
---- ----
      A = Sound RAM Address
KKKK DCBA
 
|||| ||||
  If the auto-increment flag is set, the Sound RAM address will increment (wrapping $7F->00) after every $4800
  |||| |||+- 1: Write-protect 2kB window of external RAM from $6000-$67FF (0: write enable)
  read/write.
|||| ||+-- 1: Write-protect 2kB window of external RAM from $6800-$6FFF (0: write enable)
 
|||| |+--- 1: Write-protect 2kB window of external RAM from $7000-$77FF (0: write enable)
  Sound Channel registers (inside Sound RAM):
|||| +---- 1: Write-protect 2kB window of external RAM from $7800-$7FFF (0: write enable)
 
++++------ Additionally the upper nybble must be equal to b0100 to enable writes
  regs:  "A"  "B"  "C"  "D"  "E"
 
        ------------------------------
Any value outside of the range $40-$4E will cause all PRG RAM to be read-only.
  Ch 0 - $40  $42  $44  $46  $47
 
  Ch 1 - $48  $4A  $4C  $4E  $4F
Also see [[Namco 163 audio]].
  Ch 2 - $50  $52  $54  $56  $57
 
  Ch 3 - $58  $5A  $5C  $5E  $5F
== IRQ Operation ==
  Ch 4 - $60  $62  $64  $66  $67
The IRQ is a 15-bit CPU cycle up-counter. $5000 and $5800 provide ''direct'' access to the counter itself (i.e., this isn't a reload value). Games can read and write to these registers in realtime.
  Ch 5 - $68  $6A  $6C  $6E  $6F
 
  Ch 6 - $70  $72  $74  $76  $77
The IRQ counter increments on each CPU cycle. Upon reaching $7FFF, an IRQ is fired, and it stops counting. Writing to $5000 or $5800 will acknowledge any pending IRQs.
  Ch 7 - $78  $7A  $7C  $7E  $7F
 
 
==Notes==
 
* Many older programs incorrectly identify this mapper by the name Namco 106. Some sources use the name Namcot instead of Namco, as some games and PCBs use this variation on the company name.
    "A": [FFFF FFFF]     Low 8 freq bits
* The N163 supports 8k of PRG-RAM but also has 128 bytes of internal memory. If there is a battery, then both will be battery backed. The internal memory is battery backed for several games that have no additional PRG-RAM.
    "B":  [FFFF FFFF]    Mid 8 freq bits
* If it is not battery backed, the internal RAM state will be undefined at power-on<ref>[https://forums.nesdev.org/viewtopic.php?p=285135 N163 Sound RAM Initialisation Behaviour]</ref>.
    "C": [LLLL LLFF]
* The only known difference between the Namco 129 and 163 is the 129's subtly different design of expansion audio. The only known game (Star Wars) using the Namco 129 can also be found in later runs with a Namco 163 ASIC.
        F = High 2 freq bits
* An IC labelled "160" has been found with a copy of ''Dokuganryuu Masamune'': [https://forums.nesdev.org/viewtopic.php?p=248291#p248291]
        L = Instrument Length ((64-L)*4 4-bit samples)
* Many [[INES Mapper 210]] games are incorrectly set to Mapper 019.
 
* ''Dokuganryuu Masamune'' is often thought as having WRAM. Tests have indicated however that the fourth glob is not SRAM but a [http://forums.nesdev.org/viewtopic.php?t=7727#p111097 protection circuit for the chip-internal RAM].
    "D": [AAAA AAAA]     Instrument address
 
    "E": [.... VVVV]     Volume
== See also ==
 
*[http://nesdev.org/namco106.txt Namcot 106] by goroh, fix by ZW4 and nori, english translation by nori.
 
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate.
  Special Reg $7F:
All of the below are in Japanese:
    [.EEE VVVV]
*[http://nesdev.org/namco.txt Namco mapper] by goroh
        E = Number of Enabled channels (E+1)
*[http://forums.nesdev.org/viewtopic.php?p=77795#77795 Naruko's post to the forum]
        V = Channel 7's volume control
*[http://unagi.sourceforge.jp/cgi-bin/hiki/hiki.cgi?163_namco Wiki on same]
 
*[http://d.hatena.ne.jp/na6ko/20110430/1304099059 Naruko's blog's post on the write protect register at $F800]
 
 
 
== References ==
        Instruments:
<References/>
 
 
  Instruments are in 4-bit samples.  Each byte in sound RAM represents two samples (low 4 bits being the first
[[Category:Mappers using $4020-$5FFF]][[Category:ASIC mappers]][[Category:Mappers with ROM nametables]][[Category:Mappers with cycle IRQs]][[Category:Mappers with single-screen mirroring]]
  sample, high 4 bits being the second sample).  Each channel has an address which it uses to look for the
  instrument ('A' bits in reg "D"), as well as a length indicating how many samples are in the instrument ('L'
  bits in reg "C").
 
  The instrument address is in 4-bit samples.  IE:  When the instrument address is $20, the instrument starts
  at the low 4 bits of byte address $10.  A instrument address of $41 would be the high 4 bits of byte address
  $20.
 
  Instrument Length is 4 * (64-L)  4-bit samples.  Therefore if L=59, the instrument is 20 4-bit samples long.
 
  Samples are unsigned:  '0' is low, 'F' is high.
 
  For an example waveform... given the following instrument:
 
    $A8 DC EE FF FF EF DE AC 58 23 11 00 00 10 21 53  (length of 32 ... L=56)
 
  The following waveform (a pseudo-sine wave) would be produced:
 
 
  F -      *****
  E -    **    **
  D -    *        *
  C -  *          *
  B -
  A -  *            *
  9 -
  8 - *              *
  7 -
  6 -
  5 -                  *            *
  4 -
  3 -                  *          *
  2 -                    *        *
  1 -                    **    **
  0 -                      *****
    __________________________________
 
  The waveform would continually loop this pattern
 
 
 
        Channel Disabling:
 
  Reg $7F controls the number of enabled channels.  As little as 1 or as many as all 8 channels can be enabled.
  When not all channels are enabled, the high channels are the ones being used.  That is, if only 3 channels
  are enabled, channels 5, 6, and 7 are the ones enabled, and the others are disabled.
 
  Disabling channels frees up more Sound RAM space for instruments (since the lower channels' registers are
  unused when disabled).  Also, since there are fewer channels to clock, the enabled channels are clocked more
  quickly, resulting in higher quality sound and potentially higher tones (see frequency calculation)
 
 
        Frequency Calculation:
 
  The generated tone of each channel can be calculated with the following formula:
 
                  F * CPU_CLOCK
    Hz =  --------------------------
            $F0000 * (E+1) * (64-L)*4
 
  where:
              F = the 18-bit Freq value
      CPU_CLOCK = CPU clock rate (1789772.727272 on NTSC)
              E = Enabled Channels (bits as written to reg $7F)
              L = Instrument Length (bits as written)
 
 
    Or... you can figure it as the number of CPU cycles that have to pass before the channel takes the next
  step through its instrument:
 
              $F0000 * (E+1)
  Cycs =    ------------------
                    F
 
 
    When F is 0, the channel is essentially "frozen" at it's current position and does not update (and thus,
  becomes silent).

Latest revision as of 07:30, 16 August 2024

Namco 129/163
Company Namco
Games 20 in NesCartDB
Complexity ASIC
Boards 11xF0, 111F0S
Pinout Namcot 163 family pinout
PRG ROM capacity 512K
PRG ROM window 8Kx3 + 8K fixed
PRG RAM capacity 8K
PRG RAM window 8K
CHR capacity 256K
CHR window 1Kx8 (PT) + 1Kx4 (NT)
Nametable mirroring arbitrary, up to 226 source nametables
Bus conflicts No
IRQ CPU cycle counter
Audio Yes
iNES mappers 019

iNES Mapper 019 is used to denote Famicom boards bearing the Namco 129 and Namco 163 ASICs. These chips contain 128 bytes of internal RAM that can be used either for expansion audio or, together with a battery, for 128 bytes of save RAM. Games may also come with the regular 8 KiB of additional battery-backed WRAM mapped into CPU address space at $6000-$7FFF.

In NES 2.0, the 128 bytes of internal chip RAM are not included in the PRG-RAM and PRG-NVRAM fields. NES 2.0 Mapper 19 ROM images therefore either have:

  • no battery and no WRAM: battery bit clear, PRG-RAM/PRG-NVRAM both set to zero.
  • a battery but no WRAM: battery bit set, PRG-RAM/PRG-NVRAM both set to zero. The game writes its save data into the 128 byte internal RAM.
  • a battery and WRAM: battery bit set, PRG-RAM set to zero and PRG-NVRAM set to 8192.

The NES 2.0 submapper is used to specify the mixing resistor that determines the relative volume of the expansion audio channels against the APU's audio channels:

INES Mapper 019 submapper table
Submapper # Meaning Note
0 Default Expansion sound volume unspecified
1 Deprecated Internal 128b RAM is battery backed, no external PRG-RAM is present.

No expansion sound. (Equivalent to submapper 2 with 0 in PRG-NVRAM field.)

2 No expansion sound
3 N163 expansion sound: 11.0-13.0 dB louder than NES APU
4 N163 expansion sound: 16.0-17.0 dB louder than NES APU
5 N163 expansion sound: 18.0-19.5 dB louder than NES APU


Game list

Name Chip Battery WRAM Expansion Audio NES 2.0 Submapper
Battle Fleet 163 Yes No No 2
Dragon Ninja 163 No No No 2
Digital Devil Story: Megami Tensei II 163 Yes Yes Yes 3
Dokuganryuu Masamune 163 Yes No No 2
Erika to Satoru no Yume Bouken 163 No No Yes 5
Famista '90 163 Yes No No 2
Final Lap 163 No No Yes 3
Hydlide 3: Yami kara no Houmonsha 163 Yes No No 2
Juvei Quest 163 Yes Yes No 2
Kaijuu Monogatari 163 Yes No No 2
King of Kings 163 Yes Yes Yes 5
Mappy Kids 163 No No Yes 5
Mindseeker 163 Yes No No 2
Namco Classic 163 No No No 2
Namco Classic II 163 No No Yes 3
Rolling Thunder 163 No No Yes 4
Sangokushi: Chuugen no Hasha 163 Yes Yes Yes 5
Sangokushi II: Haou no Tairiku 163 Yes Yes Yes 3
Star Wars 129 No No No 2
Youkai Douchuuki 163 No No Yes 5

Banks

  • CPU $6000-$7FFF: 8 KB PRG RAM bank, if WRAM is present
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
  • CPU $A000-$BFFF: 8 KB switchable PRG ROM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
  • CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
  • PPU $0000-$03FF: 1 KB switchable CHR bank
  • PPU $0400-$07FF: 1 KB switchable CHR bank
  • PPU $0800-$0BFF: 1 KB switchable CHR bank
  • PPU $0C00-$0FFF: 1 KB switchable CHR bank
  • PPU $1000-$13FF: 1 KB switchable CHR bank
  • PPU $1400-$17FF: 1 KB switchable CHR bank
  • PPU $1800-$1BFF: 1 KB switchable CHR bank
  • PPU $1C00-$1FFF: 1 KB switchable CHR bank
  • PPU $2000-$23FF: 1 KB switchable CHR bank
  • PPU $2400-$27FF: 1 KB switchable CHR bank
  • PPU $2800-$2BFF: 1 KB switchable CHR bank
  • PPU $2C00-$2FFF: 1 KB switchable CHR bank

These ASICs have the unusual ability to select the internal 2 KB nametable RAM as a CHR bank page, allowing it to be used as CHR RAM in combination with the existing CHR ROM.

Registers

The 163 has 19 registers within $4800-$5FFF and $8000-$FFFF. Each register occupies a range of $800 bytes, so $4800-$4FFF all refers to one register, $5000-$57FF all refers to another register, and so on.

Chip RAM Data Port ($4800-$4FFF) r/w

See Namco 163 audio.

IRQ Counter (low) ($5000-$57FF) r/w

7  bit  0
---- ----
IIII IIII
|||| ||||
++++-++++- Low 8 bits of IRQ counter

IRQ Counter (high) / IRQ Enable ($5800-$5FFF) r/w

7  bit  0
---- ----
EIII IIII
|||| ||||
|+++-++++- High 7 bits of IRQ counter
+--------- IRQ Enable: (0: disabled; 1: enabled)

CHR and NT Select ($8000-$DFFF) w

Value CPU writes Behavior
$00-$DF Always selects 1KB page of CHR-ROM
$E0-$FF If enabled by bit in $E800, use the NES's internal nametables (even values for A, odd values for B)
Write to CPU address 1KB CHR bank affected Values ≥ $E0 denote NES NTRAM if
$8000-$87FF $0000-$03FF $E800.6 = 0
$8800-$8FFF $0400-$07FF $E800.6 = 0
$9000-$97FF $0800-$0BFF $E800.6 = 0
$9800-$9FFF $0C00-$0FFF $E800.6 = 0
$A000-$A7FF $1000-$13FF $E800.7 = 0
$A800-$AFFF $1400-$17FF $E800.7 = 0
$B000-$B7FF $1800-$1BFF $E800.7 = 0
$B800-$BFFF $1C00-$1FFF $E800.7 = 0
$C000-$C7FF $2000-$23FF always
$C800-$CFFF $2400-$27FF always
$D000-$D7FF $2800-$2BFF always
$D800-$DFFF $2C00-$2FFF always

It is believed, but untested, that a game could add a normal SRAM and use it in lieu of the nametable RAM; if so, a game would be able to get 4-screen mirroring and many more pages of CHR-RAM.

PRG Select 1 ($E000-$E7FF) w

7  bit  0
---- ----
AMPP PPPP
|||| ||||
||++-++++- Select 8KB page of PRG-ROM at $8000
|+-------- Disable sound if set
+--------- Pin 22 (open collector) reflects the inverse of this value, unchanged by the address bus inputs.

If not battery backed, the internal sound RAM powers on in a random state, and similarly the N163 may power on with sound enabled. A short burst of sound due to these random settings may be heard at first power-on, before the game software manages to disable it.

PRG Select 2 / CHR-RAM Enable ($E800-$EFFF) w

7  bit  0
---- ----
HLPP PPPP
|||| ||||
||++-++++- Select 8KB page of PRG-ROM at $A000
|+-------- Disable CHR-RAM at $0000-$0FFF
|            0: Pages $E0-$FF use NT RAM as CHR-RAM
|            1: Pages $E0-$FF are the last $20 banks of CHR-ROM
+--------- Disable CHR-RAM at $1000-$1FFF
             0: Pages $E0-$FF use NT RAM as CHR-RAM
             1: Pages $E0-$FF are the last $20 banks of CHR-ROM

PRG Select 3 ($F000-$F7FF) w

7  bit  0
---- ----
CDPP PPPP
|||| ||||
||++-++++- Select 8KB page of PRG-ROM at $C000
++-------- PPU A12, A13 and these bits control pin 44

Pin 44 is high if:

  • PPU A13 is high and D is high
  • PPU A13 is low and
    • C or PPU A12 are high

Write Protect for External RAM AND Chip RAM Address Port ($F800-$FFFF) w

7  bit  0
---- ----
KKKK DCBA
|||| ||||
|||| |||+- 1: Write-protect 2kB window of external RAM from $6000-$67FF (0: write enable)
|||| ||+-- 1: Write-protect 2kB window of external RAM from $6800-$6FFF (0: write enable)
|||| |+--- 1: Write-protect 2kB window of external RAM from $7000-$77FF (0: write enable)
|||| +---- 1: Write-protect 2kB window of external RAM from $7800-$7FFF (0: write enable)
++++------ Additionally the upper nybble must be equal to b0100 to enable writes

Any value outside of the range $40-$4E will cause all PRG RAM to be read-only.

Also see Namco 163 audio.

IRQ Operation

The IRQ is a 15-bit CPU cycle up-counter. $5000 and $5800 provide direct access to the counter itself (i.e., this isn't a reload value). Games can read and write to these registers in realtime.

The IRQ counter increments on each CPU cycle. Upon reaching $7FFF, an IRQ is fired, and it stops counting. Writing to $5000 or $5800 will acknowledge any pending IRQs.

Notes

  • Many older programs incorrectly identify this mapper by the name Namco 106. Some sources use the name Namcot instead of Namco, as some games and PCBs use this variation on the company name.
  • The N163 supports 8k of PRG-RAM but also has 128 bytes of internal memory. If there is a battery, then both will be battery backed. The internal memory is battery backed for several games that have no additional PRG-RAM.
  • If it is not battery backed, the internal RAM state will be undefined at power-on[1].
  • The only known difference between the Namco 129 and 163 is the 129's subtly different design of expansion audio. The only known game (Star Wars) using the Namco 129 can also be found in later runs with a Namco 163 ASIC.
  • An IC labelled "160" has been found with a copy of Dokuganryuu Masamune: [1]
  • Many INES Mapper 210 games are incorrectly set to Mapper 019.
  • Dokuganryuu Masamune is often thought as having WRAM. Tests have indicated however that the fourth glob is not SRAM but a protection circuit for the chip-internal RAM.

See also

All of the below are in Japanese:

References

  1. ↑ N163 Sound RAM Initialisation Behaviour
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